Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

395 Questions395 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 71 โ€“ 80 of 395 Questions
Page 8 of 40
Q71
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (Programmer's View of Processor Architecture)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The __________ of a processor refers to the organization and functionalities of the registers it contains and the valid instruction set it executes.
  1. A.Programmer's view
  2. B.Hardware design
  3. C.Memory layout
  4. D.Logical interface
Q72
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (Processor Architecture Definition)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The __________ of a processor defines the software-visible organization and functionalities of the registers it contains, as well as the valid instruction set supported.
  1. A.Manufactures
  2. B.architecture
  3. C.Deal
  4. D.None of the Given
Q73
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (Instruction Operands)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The basic purpose of a computer processor is to perform machine operations, and all processor operations require __________ to act upon.
  1. A.order
  2. B.nothing
  3. C.operands
  4. D.bit
Q74
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (Four Instruction Groups)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
How many primary types of instruction groups exist in x86 assembly language?
  1. A.4
  2. B.5
  3. C.3
  4. D.2
Q75
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (EAX Sub-Register AX Mapping)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The lower 16 bits of the 32-bit extended accumulator register `EAX` are labeled and accessible as register __________.
  1. A.AX
  2. B.BX
  3. C.EAX
  4. D.none of above
Q76
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (Intel Little Endian Byte Ordering)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Intel x86 microprocessors follow which byte ordering convention for storing multi-byte data in memory?
๐Ÿ’ป assembly Snippet
; Value 0x1234 in memory (Little Endian):
; Address N: 0x34 (LSB)
; Address N+1: 0x12 (MSB)
  1. A.Little endian
  2. B.Big endian
  3. C.Both little endian and big endian
  4. D.None of the given
Q77
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (CPU Registers as Scratchpad Memory)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: Internal CPU registers are also referred to as the scratchpad RAM of the processor.
  1. A.True
  2. B.False
Q78
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (Internal Processor Registers)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
CPU registers are specialized high-speed memory storage cells located:
  1. A.Outside the processor
  2. B.Both inside and outside the processor
  3. C.Inside the processor
  4. D.None of the given
Q79
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (Register Operand Holding Function)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The basic functional purpose of a CPU register is to __________.
  1. A.Hold the operand
  2. B.Hold the operator
  3. C.Hold both the operator and operand
  4. D.None of the given
Q80
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Processor Concepts (Instruction Pointer IP Function)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The Instruction Pointer (`IP`) register holds the memory offset address of the:
  1. A.Previous instruction to be executed
  2. B.Current instruction
  3. C.Next instruction to be executed
  4. D.None of the given