Relationship between hardware architecture, machine code, and assembly language. General-purpose registers (AX, BX, CX, DX) and basic NASM syntax.
CS401 - Computer Architecture and Assembly Language Programming
Comprehensive academic curriculum covering microprocessor architecture and low-level system programming using Intel 8088/8086 and NASM. Midterm curriculum (Lectures 1–18 / Chapters 1–8) covers processor registers, segmented memory addressing (Segment x 16 + Offset), direct/indirect addressing modes, bitwise logic, stack operations, subroutines, parameter passing, and direct text video memory access (0xB800). Finalterm curriculum (Lectures 19–45 / Chapters 9–17) covers software and hardware interrupts (IVT, PIC 8259), timer programming (PIT 8253/8254), Terminate and Stay Resident (TSR) drivers, preemptive multitasking kernels, 32-bit protected mode descriptors, and C-to-assembly interfacing.
Chapters & Syllabus Units (17)
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Segmented memory architecture, segment:offset physical address calculation (Segment x 16 + Offset), immediate, direct, register, and based-indexed addressing modes.
Conditional jumps (JZ, JNZ, JC, JNC, JA, JB, JG, JL), unconditional jumps (JMP short, near, far), and CMP instruction flag impacts.
Ch 04: Bit Manipulation and Shifts
Logical operations (AND, OR, XOR, NOT, TEST), bit masking, shifts (SHL, SHR, SAL, SAR), and rotations (ROL, ROR, RCL, RCR).
Stack mechanics (LIFO, PUSH, POP, SS:SP operation), CALL and RET instructions, near vs far subroutines, and saving CPU state.
Passing parameters via registers, memory, and stack. Establishing standard stack frames using BP, local variable allocation, and calling conventions.
Ch 07: Video Memory & Screen Display
Memory-mapped I/O, VGA text mode memory at physical address 0xB800, character and attribute bytes, screen scrolling, and number printing.
Block data manipulation instructions: MOVS, STOS, LODS, SCAS, CMPS, direction flag (CLD, STD), and repeat prefixes (REP, REPE, REPNE).
Interrupt Vector Table (IVT at address 0x0000), INT instruction mechanics, IRET, BIOS service interrupts (INT 10h), and DOS services (INT 21h).
Ch 10: Hardware Interrupts and PIC 8259
Asynchronous hardware events, IN and OUT I/O port instructions, Programmable Interrupt Controller (PIC 8259), IRQ lines, and End of Interrupt (EOI).
Programmable Interval Timer (PIT 8253/8254), IRQ0 / INT 08h timer ticks, 18.2 Hz tick frequency, and clock display utilities.
Ch 12: Terminate and Stay Resident (TSR)
Background DOS system utilities, INT 21h Function 31h, calculating paragraph sizes, hooking keyboard (INT 09h), and hotkey popups.
Process Control Blocks (PCB), state preservation, cooperative multitasking kernels, and yielding CPU via software interrupts.
Timer-driven task preemption, scheduling queues, round-robin dispatching, and atomic context switching routines.
32-bit registers (EAX, EBX, ESP), Global Descriptor Table (GDT), segment selectors, 4GB linear addressing, and privilege rings.
Ch 16: Interfacing Assembly with C/C++
Calling conventions (cdecl, stdcall, fastcall), name mangling, linking NASM object files with C compilers, and returning values in EAX.
Floppy and hard disk geometry (CHS), INT 13h BIOS disk services, Master Boot Record (MBR), and device driver structures.
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice
Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.