Ch 15: 32-Bit Protected Mode Architecture

What are the types of user descriptors available in x86 protected mode? State their names.

Construct 8-byte Protected Mode Segment Descriptors in 'dd doubleword1, doubleword2' NASM assembly format given attribute parameters A = 0, P = 1, G = 0, AVL = 1, and r = 0 for: i. 32-bit, non-conforming, execute-only code segment at privilege level 2, with base address 0x00403333 and limit 0x0FFFF. ii. 32-bit, read-only data segment at privilege level 0, with base address 0x00A0BBBB and limit 0x1CCCC.

; Format: dd DWORD1, DWORD2
dd 0x3333FFFF, 0x0050D840
dd 0xBBBBCCCC, 0x005190A0

Calculate the 32-bit physical memory addresses in Protected Mode given Segment Base = 0x00A00000, Limit = 0x30000, EBX = 0x00001000, and ESI = 0x00003000 for the following memory operand accesses: i. [bx+si] ii. [ebx+esi-0x0012FD]

; Segment Base = 0x00A00000, EBX = 0x00001000, ESI = 0x00003000
mov ax, [bx+si]
mov ebx, [ebx+esi-0x0012FD]

Give the names and brief descriptions of any two Segment Descriptors used in x86 Protected Mode.

; 32-bit Code Descriptor: dd 0x0000FFFF, 0x00CF9A00
; 32-bit Data Descriptor: dd 0x0000FFFF, 0x00CF9200

Explain the complete step-by-step process required to switch an x86 processor from 16-bit Real Mode into 32-bit Protected Mode.

mov eax, cr0
or eax, 1
cli
mov cr0, eax
jmp 0x08:pstart

What is the difference between a Fault exception and a Trap exception in x86 Protected Mode architecture?

Construct the 8-byte Protected Mode Segment Descriptor in 'dd doubleword1, doubleword2' NASM assembly format for a 32-bit writable data segment at Privilege Level 2 (DPL=2), with base address 0x00B00000 and limit 0x10000. Assume attribute bits: A=1, AVL=0, P=1, r=0, G=0, D=1, E=0, and B=1.

dd 0x00000000, 0x0041D3B0

Construct the 8-byte Protected Mode Segment Descriptor in 'dd doubleword1, doubleword2' NASM assembly format for a 32-bit non-conforming, readable code segment at Privilege Level 0, with base address 0x00300000 and limit 0x0FFFF.

dd 0x0000FFFF, 0x00409A30