Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

Deep dive into 16-bit real mode memory segmentation (CS, DS, SS, ES), pointer/index registers (SP, BP, SI, DI), and calculating effective physical addresses across memory boundaries.

395 Questions395 MCQs0 Short Questions0 Long Questions

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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

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❓ MCQ📘 CS401📑 Lec 2🏷️ 2.6. Segment AssociationEasy⭐💡📄🎓VU🏛️VU

By default, the CS (Code Segment) register is implicitly associated with:

A.SS
B.BP
C.CX
D.IP

📝 Short Q📘 CS401📑 Lec 2🏷️ 2.4. Memory AddressingMedium🔁⭐💡📄🎓VU🏛️VU

Describe the 'Indexed Register Indirect + Offset' addressing mode in x86 assembly language and provide an illustrative example.

💻 assembly Snippet

mov si, 0x0100
mov ax, [si + 4]

📝 Short Q📘 CS401📑 Lec 2🏷️ 2.5. Flags RegisterEasy🔁⭐💡📄🎓VU🏛️VU

Provide valid x86 assembly instruction(s) to move the value of the FLAGS register into the AX register.

💻 assembly Snippet

pushf
pop ax

📝 Short Q📘 CS401📑 Lec 2🏷️ 2.4. Memory AddressingMedium🔁⭐💡📄🎓VU🏛️VU

Given starting offset address 0151 for Label1, list the exact byte contents of memory locations 0151 through 0158 for the following assembly data definitions: Label1: dw 8494 db 42 dw 54 dw 7500 db 01

💻 assembly Snippet

Label1: dw 8494
        db 42
        dw 54
        dw 7500
        db 01

📝 Short Q📘 CS401📑 Lec 2🏷️ 2.4. Memory AddressingEasy🔁⭐💡📄🎓VU🏛️VU

Calculate the 20-bit physical memory addresses for the following Segment:Offset pairs in Real Mode: 1. 00EA:02A4 2. 0100:AA23 3. D3B8:F222 4. 00A0:1234 5. 8FEF:0FFF

💻 assembly Snippet

; Formula: Physical Address = (Segment << 4) + Offset
; 1. 0x00EA0 + 0x02A4 = 0x01144
; 2. 0x01000 + 0xAA23 = 0x0BA23
; 3. 0xD3B80 + 0xF222 = 0xE2DA2
; 4. 0x00A00 + 0x1234 = 0x01C34
; 5. 0x8FEF0 + 0x0FFF = 0x90EEF

📝 Short Q📘 CS401📑 Lec 2🏷️ 2.4. Memory AddressingEasy🔁⭐💡📄🎓VU🏛️VU

Calculate the Effective Address (EA) generated by each of the following independent x86 assembly instructions given initial register and displacement values: BX = 0x0101, BP = 0x0222, SI = 0x1234, and var1 = 0x1771. 1. mov ax, [bx+si] 2. mov ax, [bx+100] (where 100 is in decimal) 3. mov ax, [bp+si] 4. mov ax, [var1+bp] 5. mov ax, [si+var1]

💻 assembly Snippet

; Initial Values:
; BX = 0x0101, BP = 0x0222, SI = 0x1234, var1 = 0x1771
mov ax, [bx+si]
mov ax, [bx+100]
mov ax, [bp+si]
mov ax, [var1+bp]
mov ax, [si+var1]

📝 Short Q📘 CS401📑 Lec 2🏷️ 2.5. Flags RegisterHard🔁⭐💡📄🎓VU🏛️VU

Given initial values AX = 0x1254 and BX = 0x0FFF, determine the values of the Zero Flag (ZF), Carry Flag (CF), Sign Flag (SF), and Overflow Flag (OF) after executing each of the following instructions: 1. add ax, 0xEDAB 2. add ax, bx 3. add bx, 0xF001

💻 assembly Snippet

mov ax, 0x1254
mov bx, 0x0FFF
add ax, 0xEDAB
add ax, bx
add bx, 0xF001

📝 Short Q📘 CS401📑 Lec 2🏷️ 2.5. Flags RegisterEasy🔁⭐💡📄🎓VU🏛️VU

What is the Interrupt Flag (IF) in x86 architecture, and how is it controlled?

💻 assembly Snippet

cli
; critical section
sti

❓ MCQ📘 CS401📑 Lec 2🏷️ 2.5. Flags RegisterEasy🔁⭐💡📄🎓VU🏛️VU

In x86 assembly language architecture, the Interrupt Flag (IF) in the FLAGS register is set directly by the ________.

💻 assembly Snippet

sti

A.Processor
B.Organization
C.Programmer
D.Any one can set

Q10

❓ MCQ📘 CS401📑 Lec 2🏷️ 2.5. Flags RegisterEasy🔁⭐💡📄🎓VU🏛️VU

Which x86 CPU flag has a special, dedicated role in hardware debugging and step-by-step instruction execution?

💻 assembly Snippet

pushf
pop ax
or ax, 0x0100 ; Set Trap Flag (bit 8)
push ax
popf

A.Sign Flag
B.Trap Flag
C.Interrupt Flag
D.Direction Flag

Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

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