Ch 15: 32-Bit Protected Mode Architecture

Covers transitioning from 16-bit real mode to 32-bit protected mode, setting the PE bit in CR0, constructing 8-byte segment descriptors (base, limit, access rights), and hardware memory protection rings (Ring 0 vs Ring 3).

173 Questions173 MCQs0 Short Questions0 Long Questions

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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

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Showing 21 – 30 of 173 Questions

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Q21

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Architecture (IDTR Interrupt Descriptor Table Register)Easy🔁⭐💡📄🎓VU🏛️VU

The physical memory base address and limit of the Interrupt Descriptor Table (IDT) in protected mode is stored in which register?

💻 assembly Snippet

lidt [idt_descriptor] ; Loads 48-bit pseudo-descriptor into IDTR

A.GDTR
B.IDTR
C.IVT
D.IDTT

Q22

📝 Short Q📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Architecture (Protected Mode Interrupt Handling via IDT)Medium🔁⭐💡📄🎓VU🏛️VU

Explain how hardware and software interrupts are handled in x86 Protected Mode compared to Real Mode.

💻 assembly Snippet

; IDT Gate Descriptor structure (8 bytes per entry)

Q23

📝 Short Q📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Architecture (Segment Descriptor Control Bits G, P, D, C, R, A)Medium🔁⭐💡📄🎓VU🏛️VU

Fill in the blank spaces describing the flags and control bits in an x86 Protected Mode Segment Descriptor using the provided list: (A bit, C bit, G bit, D bit, P bit, R bit): 1. The __________ defines whether the 20-bit segment limit is measured in bytes or 4 KB pages (enabling up to 4 GB segments). 2. The __________ must be set to 1 to signal that the segment is present in physical memory. 3. The __________ defines whether the code/data segment executes in 16-bit or 32-bit mode. 4. The __________ is the conforming bit. 5. The __________ signals that a code segment is readable. 6. The __________ is automatically set by the CPU whenever the segment is accessed.

💻 assembly Snippet

; Segment Descriptor Control Bits
; G=1 (4KB Granularity), P=1 (Present), D=1 (32-bit Code/Data)

Q24

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts (IDTR Interrupt Descriptor Table Register)Easy🔁⭐💡📄🎓VU🏛️VU

In x86 protected mode, the base physical address and segment limit of the Interrupt Descriptor Table (IDT) are stored in which CPU control register?

💻 assembly Snippet

lidt [idt_descriptor] ; Loads IDTR register with base and limit of IDT

A.GDTR
B.IDTR
C.IVT
D.IDTT

Q25

📝 Short Q📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts (Segment Descriptor Field Layout)Medium⭐💡📄🎓VU🏛️VU

In x86 protected mode, what information is specified by the first 16 bits (bits 0–15) of an 8-byte Segment Descriptor?

💻 assembly Snippet

; x86 Segment Descriptor Format:
; Bytes 0-1 (bits 0-15)   : Segment Limit 15..0
; Bytes 2-3 (bits 16-31)  : Base Address 15..0
; Byte 4   (bits 32-39)  : Base Address 23..16
; Byte 5   (bits 40-47)  : Access Rights Byte
; Byte 6   (bits 48-55)  : Limit 19..16 + Flags
; Byte 7   (bits 56-63)  : Base Address 31..24

Q26

📝 Short Q📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts (Granularity Types and Definition)Medium⭐💡📄🎓VU🏛️VU

How many primary types of granularity exist in software system design and x86 memory architecture? List and describe them.

Q27

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts (Segment Selector Table Indicator TI Bit)Easy🔁⭐💡📄🎓VU🏛️VU

In x86 protected mode segment selectors, what value must the Table Indicator (TI) bit contain to select the Global Descriptor Table (GDT)?

💻 assembly Snippet

; Segment Selector Layout: [Index (15..3) | TI (bit 2) | RPL (bits 1..0)]
; TI = 0 -> GDT, TI = 1 -> LDT

A.1
B.0
C.-1
D.-2

Q28

📝 Short Q📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts (Protected Mode Definition, CR0 PE Bit, 4GB Limit)Medium⭐💡📄🎓VU🏛️VU

Define x86 Protected Mode, detailing how the processor transitions into 32-bit mode, the register extensions, and memory addressing limits.

💻 assembly Snippet

mov eax, cr0
or eax, 1     ; Set Bit 0 (Protection Enable - PE)
mov cr0, eax  ; Switch to 32-bit Protected Mode

Q29

🧠 Long Problem📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts (Segment Descriptor Flags and Bits G, P, D, C, R, A)Hard⭐💡📄🎓VU🏛️VU

Fill in the blank spaces of the following x86 Segment Descriptor field passage using the correct descriptor bit identifiers from the given list: `(A bit, C bit, G bit, D bit, P bit, R bit, B bit)`. "In descriptors, the 32-bit base address is scattered across different fields for backward compatibility. The limit is stored in 20 bits, but the [Blank 1] defines whether the limit is in terms of 1-byte increments or 4KB pages, enabling a maximum segment size of 4GB. The [Blank 2] must be set to signal that this segment is present in physical memory. DPL is the Descriptor Privilege Level. The [Blank 3] defines whether the code segment executes in 16-bit or 32-bit default operand mode. The [Blank 4] is the conforming bit for code segments. The [Blank 5] signals whether a code segment is readable or data segment writable. The [Blank 6] is automatically set by hardware whenever the segment is accessed."

💻 assembly Snippet

; x86 Segment Descriptor Flags:
; Bit 55 (G) : Granularity (0 = Byte, 1 = 4KB Pages)
; Bit 54 (D) : Default operation size (0 = 16-bit, 1 = 32-bit)
; Bit 47 (P) : Present bit (1 = Memory Present)
; Bit 43 (C) : Conforming bit
; Bit 41 (R) : Readable bit
; Bit 40 (A) : Accessed bit

Q30

🧠 Long Problem📘 CS401📑 Lec 15🏷️ VESA Graphics Services and Protected Mode DisplayHard⭐💡🌟📄🎓VU🏛️VU

What are VESA services? Explain VESA video modes, INT 10h function calls, and linear frame buffer operations.

💻 assembly Snippet

mov ax, 0x4f01
mov cx, 0x4117
mov di, modeblock
int 0x10

Ch 15: 32-Bit Protected Mode Architecture

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

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