Ch 15: 32-Bit Protected Mode Architecture

Covers transitioning from 16-bit real mode to 32-bit protected mode, setting the PE bit in CR0, constructing 8-byte segment descriptors (base, limit, access rights), and hardware memory protection rings (Ring 0 vs Ring 3).

173 Questions173 MCQs0 Short Questions0 Long Questions

🎯 Exam Practice Papers

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

Showing 11 – 20 of 173 Questions

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Q11

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts and RegistersEasy🔁⭐💡📄🎓VU🏛️VU

In x86 Protected Mode, the base physical address and limit of the Interrupt Descriptor Table (IDT) are stored in which register?

💻 assembly Snippet

LIDT [idt_ptr]

A.IDTR
B.GDTR
C.IVT
D.IDTT

Q12

📝 Short Q📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts and Segment DescriptorsMedium🔁⭐💡📄🎓VU🏛️VU

In x86 Protected Mode, what information is specified in the first 16 bits (Bytes 0–1 / Word 0) of an 8-byte Segment Descriptor?

💻 assembly Snippet

struct SegmentDescriptor {
    uint16_t limit_low; // Bits 0-15: Segment Limit (0..15)
    uint16_t base_low;  // Bits 16-31: Base Address (0..15)
    // ...
};

Q13

📝 Short Q📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts and Segment DescriptorsMedium🔁⭐💡📄🎓VU🏛️VU

Explain the concept of Granularity in x86 Protected Mode Segment Descriptors, and state the types of granularity bit settings.

💻 assembly Snippet

G-bit = 0 (Byte Granularity)
G-bit = 1 (4KB Page Granularity)

Q14

📝 Short Q📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Concepts and Segment DescriptorsMedium🔁⭐💡📄🎓VU🏛️VU

Define Protected Mode in x86 processor architecture, highlighting its primary features and memory addressing mechanism.

💻 assembly Snippet

mov ax, 0x0008
mov ds, ax

Q15

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Interrupt Handling and IDTREasy🔁⭐💡📄🎓VU🏛️VU

In x86 Protected Mode, the physical base address and table limit of the Interrupt Descriptor Table (IDT) are stored in which processor register?

💻 assembly Snippet

LIDT [idt_ptr]

A.IDTR
B.GDTR
C.LDTR
D.IVT

Q16

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode and Descriptor Tables (GDT and LDT)Easy🔁⭐💡📄🎓VU🏛️VU

In x86 Protected Mode segment selector formatting, the Table Indicator (TI) bit is set to ________ to select the Global Descriptor Table (GDT).

A.0
B.1
C.-1
D.-2

Q17

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Interrupt Handling and IDTREasy🔁⭐💡📄🎓VU🏛️VU

In x86 Protected Mode, the physical base address and limit of the Interrupt Descriptor Table (IDT) are stored in which processor register?

💻 assembly Snippet

LIDT [idt_ptr]

A.IDTR
B.GDTR
C.IVT
D.IDTT

Q18

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. 32-bit Addressing and Protected Mode ArchitectureEasy🔁⭐💡📄🎓VU🏛️VU

A 32-bit address register can directly access up to ________ of physical memory address space.

A.4GB
B.2GB
C.6GB
D.8GB

Q19

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Protected Mode Interrupt Handling and IDTREasy🔁⭐💡📄🎓VU🏛️VU

In x86 Protected Mode, the linear base address and limit of the Interrupt Descriptor Table (IDT) are stored in which CPU register?

💻 assembly Snippet

LIDT [idt_ptr]

A.IDTR
B.GDTR
C.IVT
D.IDTT

Q20

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. Comparison of Microprocessors (SPARC RISC Fixed 32-Bit Instruction Size)Easy🔁⭐💡📄🎓VU🏛️VU

Sun SPARC processors utilize a fixed instruction word size of __________ bits.

A.16bit
B.32bit
C.64bit
D.8bit

Ch 15: 32-Bit Protected Mode Architecture

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

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