Ch 15: 32-Bit Protected Mode Architecture

173 Questions173 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

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Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

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Showing 41 – 50 of 173 Questions
Page 5 of 18
Q41
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 15🏷️ Processor Evolution and Backward CompatibilityEasyβ­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
The Intel 80386 processor is ________ compatible with the earlier 16-bit iAPX88 (8088/8086) processor architecture.
  1. A.Downward (Backward)
  2. B.Upward (Forward)
  3. C.Both downward and upward
  4. D.Neither
Q42
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 15🏷️ Protected Mode IDTR Register ArchitectureMediumπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
In x86 Protected Mode, what is the total bit size of the Interrupt Descriptor Table Register (IDTR)?
πŸ’» assembly Snippet
lidt [idtr_buffer]
  1. A.8 bits
  2. B.16 bits
  3. C.32 bits
  4. D.48 bits
Q43
πŸ“ Short QπŸ“˜ CS401πŸ“‘ Lec 15🏷️ Protected Mode System Descriptors and GatesMediumπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
Define a System Descriptor in x86 Protected Mode architecture and contrast it with standard code/data segment descriptors.
πŸ’» assembly Snippet
dd 0x00000000, 0x00008500
Q44
πŸ“ Short QπŸ“˜ CS401πŸ“‘ Lec 15🏷️ VESA Graphics Services and Return CodesEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
Which CPU register is used by BIOS INT 10h VESA functions (VBE 2.0) to return completion status?
πŸ’» assembly Snippet
mov ax, 0x4F00
mov di, buffer
int 0x10
Q45
πŸ“ Short QπŸ“˜ CS401πŸ“‘ Lec 15🏷️ Global Descriptor Table (GDT) and GDTR ArchitectureMediumπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
Complete the following statement regarding Global Descriptor Table (GDT) architecture in x86 Protected Mode: 'The GDT itself is an array of descriptors where each descriptor is an ____-byte entry. The base and limit of GDT is stored in a ____-bit register called the ____. This register is loaded with a special instruction ____ and is given a memory address from where the 48 bits are fetched.'
πŸ’» assembly Snippet
lgdt [gdt_ptr]
Q46
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 15🏷️ Protected Mode IDTR Register ArchitectureEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
The physical base address and segment limit of the Interrupt Descriptor Table (IDT) in protected mode are stored in which 48-bit processor register?
πŸ’» assembly Snippet
lidt [idtr_buffer]
  1. A.GDTR
  2. B.IDTR
  3. C.IVT
  4. D.IDTT
Q47
πŸ“ Short QπŸ“˜ CS401πŸ“‘ Lec 15🏷️ Protected Mode Segment Descriptors and Field LayoutMediumπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
What do the first 16 bits (Bits 0–15) of an 8-byte x86 Protected Mode Segment Descriptor represent?
πŸ’» assembly Snippet
dd 0x0000FFFF, 0x00CF9A00
Q48
πŸ“ Short QπŸ“˜ CS401πŸ“‘ Lec 15🏷️ Segment Descriptor Granularity (G Bit)MediumπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
Explain the concept of Granularity in x86 Protected Mode segment descriptors and describe the two types of Granularity controlled by the G bit.
πŸ’» assembly Snippet
; G = 0 -> Limit in Bytes
; G = 1 -> Limit in 4KB Pages
Q49
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 15🏷️ 32-Bit Protected Mode System Registers (IDTR)MediumπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
In x86 Protected Mode, which processor register stores the physical base address and limit of the Interrupt Descriptor Table (IDT)?
πŸ’» assembly Snippet
lidt [idtreg]
  1. A.GDTR
  2. B.IDTR
  3. C.IVT
  4. D.IDTT
Q50
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 15🏷️ Protected Mode Segment Selectors and Descriptor Tables (GDT/LDT)MediumπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
In x86 Protected Mode, what value must the Table Indicator (TI) bit be set to in a segment selector to access the Global Descriptor Table (GDT)?
  1. A.1 (LDT)
  2. B.0 (GDT)
  3. C.-1
  4. D.-2