Ch 15: 32-Bit Protected Mode Architecture

Covers transitioning from 16-bit real mode to 32-bit protected mode, setting the PE bit in CR0, constructing 8-byte segment descriptors (base, limit, access rights), and hardware memory protection rings (Ring 0 vs Ring 3).

173 Questions173 MCQs0 Short Questions0 Long Questions

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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

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Q171

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.1. IntroductionEasy🔁⭐💡📄🎓VU🏛️VU

The 16-bit value loaded into a segment register when the x86 processor operates in protected mode is called a:

💻 assembly Snippet

mov ax, 0x10  ; 0x10 is a segment selector
mov ds, ax

A.Segment descriptor
B.Segment selector
C.Global descriptor table
D.Protected register

Q172

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.2. 32bit ProgrammingEasy🔁⭐💡📄🎓VU🏛️VU

In x86 32-bit architecture, FS and GS are two additional ________ introduced to support extra data segment access.

💻 assembly Snippet

mov ax, 0x10
mov fs, ax
mov gs, ax

A.Segment registers
B.Segment selectors
C.Stack pointers
D.Register pointers

Q173

❓ MCQ📘 CS401📑 Lec 15🏷️ 15.4. Interrupt HandlingEasy🔁⭐💡📄🎓VU🏛️VU

In x86 protected mode system architecture, what does the acronym IDT stand for?

💻 assembly Snippet

lidt [idtreg]

A.Interrupt Descriptor Table
B.Individual Descriptor Table
C.Inline Data Table
D.Internal Descriptor Table

Ch 15: 32-Bit Protected Mode Architecture

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

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