Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

395 Questions395 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
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Showing 231 โ€“ 240 of 395 Questions
Page 24 of 40
Q231
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Intel 8088 Microprocessor ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The Intel 8088 microprocessor is classified as a __________ architecture based on its internal register width.
  1. A.16-bit processor
  2. B.32-bit processor
  3. C.64-bit processor
  4. D.128-bit processor
Q232
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Control Flags vs Status FlagsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which group of processor flags functions purely as control flags and is NOT modified to reflect mathematical operation results?
  1. A.Carry Flag, Interrupt Flag, and Trap Flag
  2. B.Direction Flag, Interrupt Flag, and Trap Flag
  3. C.Direction Flag, Overflow Flag, and Trap Flag
  4. D.Direction Flag, Interrupt Flag, and Sign Flag
Q233
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Data Definition Directives (db)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which assembly language directive is used to reserve or initialize an 8-bit (1 byte) memory location?
๐Ÿ’ป assembly Snippet
var1: db 10
  1. A.db (Define Byte)
  2. B.dw (Define Word)
  3. C.dn (Define Nibble)
  4. D.dd (Define Double Word)
Q234
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Assembly Instruction Operands (Source vs Destination)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In the assembly instruction 'MOV AX, 5', what role does the constant value '5' play?
๐Ÿ’ป assembly Snippet
mov ax, 5
  1. A.Source operand
  2. B.Destination operand
  3. C.Memory operand
  4. D.Register operand
Q235
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Instruction Operands CountEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
How many total operands are present in the assembly instruction 'MOV AX, 5'?
๐Ÿ’ป assembly Snippet
mov ax, 5
  1. A.1 operand
  2. B.2 operands
  3. C.3 operands
  4. D.4 operands
Q236
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Control Flags vs Status FlagsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which group of CPU status/control flags is NOT used or modified by arithmetic and mathematical operations?
  1. A.Carry, Interrupt, and Trap flags
  2. B.Direction, Interrupt, and Trap flags
  3. C.Direction, Overflow, and Trap flags
  4. D.Direction, Interrupt, and Sign flags
Q237
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Direct Memory Addressing SyntaxEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Write an assembly language instruction to copy the contents of the memory word at offset address 0x0025 within the current Data Segment into register AX.
๐Ÿ’ป assembly Snippet
mov ax, [0x0025]
Q238
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 8088 Register File (CX Count Register)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In x86 processor architecture, register CX is primarily designated as the:
๐Ÿ’ป assembly Snippet
mov cx, 10
loop my_loop
  1. A.Count register
  2. B.Data register
  3. C.Index register
  4. D.Base register
Q239
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Stack Physical Addressing (SS:SP)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In 8088 real mode, the physical memory address of the current stack top is computed using which segment and offset register combination?
  1. A.SS:SI combination
  2. B.SS:SP combination
  3. C.ES:BP combination
  4. D.ES:SP combination
Q240
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Physical Memory Addressing (20-Bit Address Bus)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
How many address bus bits/lines are required to directly address 1 MB (1 Megabyte) of physical memory?
  1. A.16 bits
  2. B.32 bits
  3. C.Depends on processor architecture
  4. D.20 bits