Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

Deep dive into 16-bit real mode memory segmentation (CS, DS, SS, ES), pointer/index registers (SP, BP, SI, DI), and calculating effective physical addresses across memory boundaries.

395 Questions395 MCQs0 Short Questions0 Long Questions

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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

Showing 171 – 180 of 395 Questions

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Q171

📝 Short Q📘 CS401📑 Lec 2🏷️ Implied Operands in x86 ArchitectureMedium🔁⭐💡📄🎓VU🏛️VU

Define an implied operand in assembly language programming and give an example.

💻 assembly Snippet

stosb
mul bl

Q172

❓ MCQ📘 CS401📑 Lec 2🏷️ General Purpose Registers (CX Counter Register)Easy🔁⭐💡📄🎓VU🏛️VU

In x86 assembly language, what is the primary architectural role of register CX?

💻 assembly Snippet

mov cx, 10
loop label1

A.Counter register
B.Flag register
C.Base register
D.Destination register

Q173

❓ MCQ📘 CS401📑 Lec 2🏷️ Logical Address Pairing (CS:IP)Easy🔁⭐💡📄🎓VU🏛️VU

In x86 segmented architecture, the Code Segment (CS) register is implicitly paired with which pointer register to form the complete logical execution address?

A.Stack Pointer (SS)
B.Base Pointer (BP)
C.Count Register (CX)
D.Instruction Pointer (IP)

Q174

❓ MCQ📘 CS401📑 Lec 2🏷️ Assembly Instruction Operands and SyntaxEasy🔁⭐💡📄🎓VU🏛️VU

How many operands are specified in the assembly instruction 'MOV AX, 5'?

💻 assembly Snippet

mov ax, 5

A.1 operand
B.2 operands
C.3 operands
D.4 operands

Q175

❓ MCQ📘 CS401📑 Lec 2🏷️ Effective Address CalculationEasy🔁⭐💡📄🎓VU🏛️VU

All offset addressing mechanisms in the Intel iAPX88 architecture calculate and return a 16-bit offset number called the __________.

💻 assembly Snippet

mov ax, [bx + si + 4]

A.Effective address
B.Faulty address
C.Indirect address
D.Direct address

Q176

❓ MCQ📘 CS401📑 Lec 2🏷️ Count Register (CX) and Loop MechanicsEasy🔁⭐💡📄🎓VU🏛️VU

In x86 assembly language, the CX register is normally used as a __________ register.

💻 assembly Snippet

mov cx, 10
label1:
    ; loop body
    loop label1

A.Source register
B.Counter register
C.Index register
D.Pointer register

Q177

❓ MCQ📘 CS401📑 Lec 2🏷️ Index Registers (SI and DI) and Memory AccessEasy🔁⭐💡📄🎓VU🏛️VU

In x86 assembly language, what are index registers (SI and DI) primarily used to store?

💻 assembly Snippet

mov si, buffer_offset
mov al, [si]

A.Numeric data values only
B.Intermediate calculation results
C.Memory offset addresses
D.Both data values and memory addresses

Q178

❓ MCQ📘 CS401📑 Lec 2🏷️ Flags Register and Bit-Wise SignificanceEasy🔁⭐💡📄🎓VU🏛️VU

In which CPU register do individual bits operate independently and individually to represent distinct processor statuses or controls?

A.Index register
B.Base register
C.Flags register
D.Accumulator register

Q179

❓ MCQ📘 CS401📑 Lec 2🏷️ Count Register (CX) MechanicsEasy🔁⭐💡📄🎓VU🏛️VU

In x86 assembly language architecture, what is the primary structural role of register CX?

💻 assembly Snippet

mov cx, 5
loop label

A.Count register
B.Data register
C.Index register
D.Base register

Q180

❓ MCQ📘 CS401📑 Lec 2🏷️ CPU Registers and Internal ArchitectureEasy🔁⭐💡📄🎓VU🏛️VU

Which of the following statements is NOT true regarding CPU registers?

A.Their operation is very much like memory
B.Intermediate results may also be stored in registers
C.They are also called scratch pad RAM
D.None of the given options

Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

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