Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

395 Questions395 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 181 โ€“ 190 of 395 Questions
Page 19 of 40
Q181
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Default Segment Association for BP RegisterEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The instruction 'MOV [BP], AL' moves the one-byte content of register AL to the memory address contained in BP within which default segment?
๐Ÿ’ป assembly Snippet
mov [bp], al
  1. A.Stack segment
  2. B.Code segment
  3. C.Data segment
  4. D.Extra segment
Q182
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Assembly Language Syntax and LabelsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In the assembly language statement 'total: dw 0', what structural assembly component is 'total'?
๐Ÿ’ป assembly Snippet
total: dw 0
  1. A.Literal
  2. B.Variable
  3. C.Label
  4. D.Starting point
Q183
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Registers as Scratchpad MemoryEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
CPU registers function like scratchpad RAM inside the processor, and their internal operation is very similar to normal __________.
  1. A.Numbers
  2. B.Operations
  3. C.Memory cells
  4. D.Buses
Q184
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Computer Operations and OperandsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The fundamental purpose of a computer system is to perform operations, and every operation requires __________.
  1. A.Execution order
  2. B.No inputs
  3. C.Operands
  4. D.Bit flags
Q185
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Accumulator and Processor Word SizeEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Every processor features a central working register called the accumulator. The native word size of a processor is defined by the width of its __________.
  1. A.Accumulator
  2. B.Data bus
  3. C.Address bus
  4. D.Memory cell
Q186
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Address-Holding Registers (Pointer, Index, and Base Registers)Medium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which functional group of CPU registers does not hold general data values, but instead holds effective memory offset addresses?
๐Ÿ’ป assembly Snippet
mov ax, [bx + si]
  1. A.Pointer, Segment, or Base Register
  2. B.Pointer, Index, or Base Register
  3. C.General Data Registers
  4. D.Instruction Pointer only
Q187
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Instruction Pointer (IP) FunctionalityEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The Program Counter (Instruction Pointer - IP) holds the memory address of the next instruction to be __________.
  1. A.Executed
  2. B.Called
  3. C.Deleted
  4. D.Copied
Q188
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ x86 Instruction Group ClassificationEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
How many main functional groups of instructions exist in x86 assembly language architecture?
  1. A.4 groups
  2. B.5 groups
  3. C.3 groups
  4. D.2 groups
Q189
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Data Movement Instruction DefinitionEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Is the following statement true or false: 'Data movement instructions are used to copy or transfer data from one location to another'?
๐Ÿ’ป assembly Snippet
mov ax, bx
  1. A.True
  2. B.False
Q190
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ Data Movement Instructions (MOV)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which functional instruction group does the assembly instruction 'MOV' belong to?
๐Ÿ’ป assembly Snippet
mov ax, 5
  1. A.Arithmetic and Logic Instructions
  2. B.Data Movement Instructions
  3. C.Program Control Instructions
  4. D.Special Instructions