Ch 08: String Instructions and Primitives

Comprehensive study of x86 string primitives operating across DS:SI and ES:DI, hardware-accelerated memory copy, screen clearing via STOSW, string length calculation via SCASB, and string comparison via CMPSB.

307 Questions307 MCQs0 Short Questions0 Long Questions

🎯 Exam Practice Papers

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

Showing 201 – 210 of 307 Questions

Page 21 of 31

Q201

📝 Short Q📘 CS401📑 Lec 8🏷️ Hooking IVT Vectors for Single-Step and Breakpoint DebuggingHard🔁⭐💡🌟📄🎓VU🏛️VU

Complete the missing assembly code lines to hook the single-step trap handler (trapisr), breakpoint handler (debugisr), and keyboard handler (kbisr) into the Interrupt Vector Table (IVT), and explain how the Trap Flag (TF) is set on the stack to enable step-by-step execution.

💻 assembly Snippet

start:
    xor ax, ax
    mov es, ax              ; point es to IVT base
    mov word [es:1*4], trapisr ; store offset at n*4
    mov [es:1*4+2], cs      ; store segment at n*4+2
    mov word [es:3*4], debugisr ; store offset at n*4
    mov [es:3*4+2], cs      ; store segment at n*4+2
    cli                     ; disable interrupts
    mov word [es:9*4], kbisr ; store offset at n*4
    mov [es:9*4+2], cs      ; store segment at n*4+2
    sti                     ; enable interrupts

Q202

❓ MCQ📘 CS401📑 Lec 8🏷️ Keyboard Interrupt Line (IRQ 1 / INT 9)Easy🔁⭐💡📄🎓VU🏛️VU

Which hardware Interrupt Request (IRQ) line is connected to the keyboard controller?

A.IRQ 0
B.IRQ 1
C.IRQ 2
D.IRQ 3

Q203

❓ MCQ📘 CS401📑 Lec 8🏷️ Floppy Disk Controller IRQ Assignment (IRQ 6)Easy🔁⭐💡📄🎓VU🏛️VU

Which hardware Interrupt Request (IRQ) line is reserved for the Floppy Disk Drive controller?

A.IRQ 4
B.IRQ 5
C.IRQ 6
D.IRQ 7

Q204

❓ MCQ📘 CS401📑 Lec 8🏷️ Divide-by-Zero Hardware Exception (INT 0)Easy🔁⭐💡📄🎓VU🏛️VU

When an arithmetic division by zero occurs during program execution, how is the 'Divide by Zero' exception (INT 0) triggered?

A.By calling INT 0 explicitly in software
B.By calling INT 1 explicitly in software
C.By calling INT 2 explicitly in software
D.This interrupt is generated automatically by processor hardware

Q205

❓ MCQ📘 CS401📑 Lec 8🏷️ Interrupt Request (IRQ) ConflictsEasy🔁⭐💡📄🎓VU🏛️VU

What condition occurs when two distinct peripheral hardware devices in a computer system attempt to utilize the same IRQ line simultaneously?

A.An IRQ Collision
B.An IRQ Conflict
C.An IRQ Crash
D.An IRQ Blockage

Q206

📝 Short Q📘 CS401📑 Lec 8🏷️ Breakpoint Interrupt Service Routine (INT 3) ImplementationHard🔁⭐💡🌟📄🎓VU🏛️VU

Write the assembly language code for a Breakpoint Interrupt Service Routine (INT 3 ISR) that saves register context, restores the original opcode at the breakpoint address, displays register values on screen, enables the Trap Flag (TF) on the stack, and waits for keypress confirmation.

💻 assembly Snippet

debugISR:
    push bp
    mov bp, sp
    dec word [bp+2]

Q207

📝 Short Q📘 CS401📑 Lec 8🏷️ Interrupt Vector Table (IVT) Vector InstallationMedium🔁⭐💡📄🎓VU🏛️VU

Write the assembly language code sequence to install custom interrupt service routines for INT 1 (trapisr), INT 3 (debugisr), and INT 9 (kbisr) into the Interrupt Vector Table (IVT) starting at segment 0x0000.

💻 assembly Snippet

mov [es:1*4+2], cs
mov word [es:3*4], debugisr
mov [es:3*4+2], cs
cli
mov word [es:9*4], kbisr
mov [es:9*4+2], cs
sti

Q208

❓ MCQ📘 CS401📑 Lec 8🏷️ Single-Step Exception (INT 1) and Trap FlagEasy🔁⭐💡📄🎓VU🏛️VU

Which processor interrupt vector is generated after every instruction execution when the Trap Flag (TF = 1) is set for single-step debugging?

A.INT 0
B.INT 1
C.INT 2
D.INT 3

Q209

❓ MCQ📘 CS401📑 Lec 8🏷️ Arithmetic Overflow Exception (INT 4)Easy🔁⭐💡📄🎓VU🏛️VU

Which software interrupt vector is reserved by Intel for handling Arithmetic Overflow exceptions generated by the INTO instruction?

💻 assembly Snippet

into

A.INT 1
B.INT 2
C.INT 3
D.INT 4

Q210

❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC Hardware IRQ Input LinesEasy🔁⭐💡📄🎓VU🏛️VU

In the 8259 Programmable Interrupt Controller (PIC), the IRQ lines on the master chip are configured as:

A.Eight Input signals (IRQ 0 - IRQ 7)
B.One Input signal
C.Eight Output signals
D.One Output signal

Ch 08: String Instructions and Primitives

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

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