Ch 08: String Instructions and Primitives

Comprehensive study of x86 string primitives operating across DS:SI and ES:DI, hardware-accelerated memory copy, screen clearing via STOSW, string length calculation via SCASB, and string comparison via CMPSB.

307 Questions307 MCQs0 Short Questions0 Long Questions

🎯 Exam Practice Papers

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

Showing 221 – 230 of 307 Questions

Page 23 of 31

Q221

❓ MCQ📘 CS401📑 Lec 8🏷️ Serial Port Interrupt Request Assignment (IRQ 4 / COM1)Easy🔁⭐💡📄🎓VU🏛️VU

Which hardware Interrupt Request (IRQ) line is connected to serial communication port COM1?

A.IRQ 4
B.IRQ 5
C.IRQ 6
D.IRQ 7

Q222

❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC Control Port 20h and Data Port 21hEasy🔁⭐💡📄🎓VU🏛️VU

In the 8259 Programmable Interrupt Controller (PIC), which I/O port address functions as the primary Control / Command port?

💻 assembly Snippet

mov al, 0x20
out 0x20, al

A.Port 19h
B.Port 20h
C.Port 21h
D.Port 22h

Q223

❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC I/O Port Address MappingEasy🔁⭐💡📄🎓VU🏛️VU

How many consecutive I/O port addresses does a single 8259 Programmable Interrupt Controller (PIC) chip occupy in x86 isolated I/O address space?

A.1 port address
B.2 port addresses (e.g., 20h and 21h for Master PIC)
C.4 port addresses
D.8 port addresses

Q224

❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC Hardware Input and Output SignalsEasy🔁⭐💡📄🎓VU🏛️VU

The 8259 Programmable Interrupt Controller (PIC) interface consists of how many input hardware request lines and CPU interrupt output signals?

A.One input signal and eight output signals
B.One input signal and one output signal
C.Eight input signals and one output signal
D.Eight input signals and eight output signals

Q225

📝 Short Q📘 CS401📑 Lec 8🏷️ Single-Step Interrupt (INT 1) and IVT Vector Memory MappingMedium🔁⭐💡📄🎓VU🏛️VU

For what purpose is 'INT 1' reserved in x86 processor architecture? Specify its exact physical memory byte locations in the Interrupt Vector Table (IVT).

Q226

📝 Short Q📘 CS401📑 Lec 8🏷️ Single-Step Debugging and Trap Flag (INT 1)Easy🔁⭐💡📄🎓VU🏛️VU

Explain the purpose of the Single-Step Interrupt (INT 1) and how the Trap Flag (TF) enables step-by-step program debugging.

Q227

📝 Short Q📘 CS401📑 Lec 8🏷️ Interrupt Service Routine (ISR) and IRET Instruction MechanicsMedium🔁⭐💡📄🎓VU🏛️VU

Explain the purpose of an Interrupt Service Routine (ISR) and describe how the IRET (Interrupt Return) instruction differs from a standard RET instruction.

💻 assembly Snippet

my_isr:
    push ax
    ; ISR execution body
    pop ax
    iret

Q228

❓ MCQ📘 CS401📑 Lec 8🏷️ Control Unit Role in System Bus SignalingEasy🔁⭐💡📄🎓VU🏛️VU

Transmitting appropriate control and timing signals (such as MEMR or MEMW) over the control bus to memory is the responsibility of which system component?

A.Control Unit (CU) / Processor
B.Memory Management Unit
C.Data Bus
D.ALU

Q229

❓ MCQ📘 CS401📑 Lec 8🏷️ Flag Register Structure and MeaningEasy🔁⭐💡📄🎓VU🏛️VU

A processor register where each individual bit has a distinct, independent meaning representing a CPU status condition or control setting is called the:

A.Flag Register
B.Accumulator Register
C.Index Register
D.Segment Register

Q230

❓ MCQ📘 CS401📑 Lec 8🏷️ 8088 Memory Addressing Modes CountEasy🔁⭐💡📄🎓VU🏛️VU

How many distinct modes of memory access (addressing modes) are supported by the iAPX88 (8088) processor?

A.5
B.7
C.9
D.12

Ch 08: String Instructions and Primitives

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

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