Ch 08: String Instructions and Primitives

Comprehensive study of x86 string primitives operating across DS:SI and ES:DI, hardware-accelerated memory copy, screen clearing via STOSW, string length calculation via SCASB, and string comparison via CMPSB.

307 Questions307 MCQs0 Short Questions0 Long Questions

🎯 Exam Practice Papers

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

Showing 191 – 200 of 307 Questions

Page 20 of 31

Q191

📝 Short Q📘 CS401📑 Lec 8🏷️ Single-Step Debug Interrupt (INT 1)Easy🔁⭐💡📄🎓VU🏛️VU

For what specific purpose is Software Interrupt 1 (INT 1) reserved in x86 processor architecture?

Q192

📝 Short Q📘 CS401📑 Lec 8🏷️ Disabling Keyboard Interrupt via 8259 PIC Port 21hMedium🔁⭐💡📄🎓VU🏛️VU

Write a 5-instruction assembly language program to disable (mask) the keyboard hardware interrupt (IRQ 1) using the 8259 Programmable Interrupt Controller (PIC) Interrupt Mask Register (IMR).

💻 assembly Snippet

in al, 0x21
or al, 0x02
out 0x21, al

Q193

❓ MCQ📘 CS401📑 Lec 8🏷️ Non-Maskable Interrupt (INT 2)Easy🔁⭐💡📄🎓VU🏛️VU

Which x86 processor interrupt vector is dedicated to handling the hardware Non-Maskable Interrupt (NMI)?

A.INT 2
B.INT 3
C.INT 0
D.INT 1

Q194

❓ MCQ📘 CS401📑 Lec 8🏷️ Serial Communication IRQ Assignments (COM 2 / IRQ 3)Easy🔁⭐💡📄🎓VU🏛️VU

Which hardware Interrupt Request (IRQ) line is connected to Serial Port COM 2 in standard IBM PC architecture?

A.IRQ 0
B.IRQ 1
C.IRQ 2
D.IRQ 3

Q195

❓ MCQ📘 CS401📑 Lec 8🏷️ System Timer Tick Interval (55 ms)Easy🔁⭐💡📄🎓VU🏛️VU

What is the approximate time interval between two consecutive clock ticks generated by the Programmable Interval Timer (PIT IRQ 0)?

A.40 ms
B.45 ms
C.50 ms
D.55 ms

Q196

❓ MCQ📘 CS401📑 Lec 8🏷️ Single-Step Exception (INT 1) vs Divide Overflow (INT 0)Medium🔁⭐💡📄🎓VU🏛️VU

In x86 processor architecture, the single-step interrupt (INT 1) is classified as an internal CPU exception, making it functionally similar to which other exception?

A.Hardware interrupt
B.Like divide-by-zero interrupt (INT 0)
C.Like divide-by-1 interrupt
D.Software interrupt

Q197

❓ MCQ📘 CS401📑 Lec 8🏷️ Programmable Interval Timer and IRQ 0Easy🔁⭐💡📄🎓VU🏛️VU

Which hardware Interrupt Request (IRQ) line is driven directly by the system Programmable Interval Timer (PIT)?

A.IRQ 0
B.IRQ 1
C.IRQ 2
D.IRQ 3

Q198

❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC Command Port (Port 20h)Easy🔁⭐💡📄🎓VU🏛️VU

In the 8259 Programmable Interrupt Controller (PIC), which I/O port address is designated as the primary Control Port?

💻 assembly Snippet

out 0x20, al

A.Port 19h
B.Port 20h
C.Port 21h
D.Port 22h

Q199

📝 Short Q📘 CS401📑 Lec 8🏷️ INT 3 Breakpoint Interrupt MechanicsMedium🔁⭐💡📄🎓VU🏛️VU

Describe the functionality and special characteristics of the INT 3 Debug Exception interrupt in x86 assembly language.

💻 assembly Snippet

int 3

Q200

📝 Short Q📘 CS401📑 Lec 8🏷️ Breakpoint Interrupt Service Routine (INT 3 ISR)Hard🔁⭐💡📄🎓VU🏛️VU

Write the assembly language code for a Breakpoint Interrupt Handler (INT 3 ISR) that reads the saved register state, decrements the return address to point back to the breakpoint instruction, and prepares for opcode restoration.

💻 assembly Snippet

debugISR:
    push bp
    mov bp, sp
    dec word [bp+2]

Ch 08: String Instructions and Primitives

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

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