Ch 08: String Instructions and Primitives

307 Questions307 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 301 โ€“ 307 of 307 Questions
Page 31 of 31
Q301
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.2. Interrupt Vector TableEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
To hook an interrupt in x86 assembly, the programmer modifies the corresponding ________ entry inside the Interrupt Vector Table (IVT).
  1. A.SX register
  2. B.Interrupt vector
  3. C.AX register
  4. D.BX register
Q302
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which interrupt vector corresponds to the Non-Maskable Interrupt (NMI)?
  1. A.INT 0
  2. B.INT 1
  3. C.INT 2
  4. D.INT 3
Q303
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which instruction returns execution from an Interrupt Service Routine (ISR) by popping IP, CS, and FLAGS off the stack?
๐Ÿ’ป assembly Snippet
iret
  1. A.RET n
  2. B.REZA
  3. C.REPE
  4. D.IRET
Q304
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.2. Interrupt Vector TableEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Interrupt hooking is accomplished by changing the address contained in the interrupt ________.
  1. A.SX register
  2. B.Interrupt vector
  3. C.AX register
  4. D.BX register
Q305
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.3. Programmable Interrupt Controller (8259)Medium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
On IBM PC/AT architecture using dual 8259A PICs, which IRQ line is reserved for cascading the secondary (slave) interrupt controller?
  1. A.IRQ 0
  2. B.IRQ 1
  3. C.IRQ 2
  4. D.IRQ 3
Q306
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.3. Programmable Interrupt Controller (8259)Medium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The 8259 Programmable Interrupt Controller uses I/O ports 0x20 and 0x21. Port 0x20 functions as the Control Port, while Port 0x21 serves as the:
๐Ÿ’ป assembly Snippet
in al, 0x21  ; Read IMR from port 0x21
  1. A.Interrupt Mask Register (IMR)
  2. B.Interrupt Port
  3. C.Output Port
  4. D.Input Port
Q307
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The 8088 processor classifies interrupts into how many fundamental primary categories?
  1. A.2 (Software Interrupts and Hardware Interrupts)
  2. B.3
  3. C.4
  4. D.5