Ch 01: Introduction to Assembly Language

387 Questions387 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 51 โ€“ 60 of 387 Questions
Page 6 of 39
Q51
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Byte Definition 8-Bit)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
A standard memory cell is an $n$-bit location used to store data. A location containing __________ bits is normally called a byte.
  1. A.4-bit
  2. B.8-bit
  3. C.6-bit
  4. D.80-bit
Q52
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Memory Dimensions and Cell Width)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In computer memory organization, which two primary parameters completely define the capacity and structure of a memory unit?
  1. A.Cell width and number of cells
  2. B.cell number and width of the cells
  3. C.width
  4. D.Height
Q53
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Memory Dimensions and Bit Width)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When defining memory dimensions (e.g., $N \times W$), the first dimension ($N$) specifies the total number of memory cells, while the second dimension ($W$) specifies how many __________ are in a single memory cell.
  1. A.bits
  2. B.bytes
  3. C.words
  4. D.registers
Q54
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Data Bus and Cell Width Alignment)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The __________ memory operation requires matching the size of the data bus to the memory cell width for maximum bus efficiency.
  1. A.Normal
  2. B.Best and simplest
  3. C.first
  4. D.None of the Given
Q55
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Parallel Memory Bus Transfers)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In computer memory access architecture, data transfer between the processor and memory cells across the system data bus is performed in __________ mode.
  1. A.parallel
  2. B.Vertical
  3. C.long
  4. D.short
Q56
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Processor Control Bus Signals)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The control bus is the physical signal pathway, but the responsibility of generating and driving appropriate control signals (e.g., READ / WRITE) onto the control bus rests with the __________.
  1. A.Data Bus
  2. B.processor
  3. C.Address Bus
  4. D.None of the Given
Q57
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Program Definition)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: A computer program is defined as an ordered set of instructions designed for execution by the processor.
  1. A.TRUE
  2. B.FALSE
Q58
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Byte Definition 8-Bit)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
A memory cell is an $n$-bit location used to store data. A cell containing __________ bits is normally called a byte.
  1. A.4-bit
  2. B.8-bit
  3. C.6-bit
  4. D.80-bit
Q59
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Parallel Memory Bus Transfers)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When defining memory dimensions, memory transfers between processor and memory cells across the system data bus occur in __________ mode.
  1. A.parallel
  2. B.Vertical
  3. C.long
  4. D.short
Q60
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer Architecture (Data Bus and Cell Width Alignment)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The __________ memory operation requires matching the size of the data bus to the memory cell width for maximum transfer efficiency.
  1. A.Normal
  2. B.Best and simplest
  3. C.first
  4. D.None of the Given