Ch 01: Introduction to Assembly Language

387 Questions387 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 71 โ€“ 80 of 387 Questions
Page 8 of 39
Q71
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Assembly Language (Assembly Source File Extension.asm)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is the standard file extension for an assembly language source code file?
  1. A..doc
  2. B..com
  3. C..lst
  4. D..asm
Q72
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Assembly Language (Low-Level Language Definition)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: Assembly language is NOT classified as a low-level language.
  1. A.True
  2. B.False
Q73
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Bus Architecture (Three Primary System Buses)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which three system buses enable communication between the processor, physical memory, and I/O devices?
  1. A.address bus, data bus and data bus
  2. B.addressing bus, data bus and data bus
  3. C.address bus, datamove bus and data bus
  4. D.address bus, data bus and control bus
Q74
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Bus Architecture (Unidirectional Address Bus)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: The system address bus is unidirectional, and physical memory addresses always travel from the processor to memory.
  1. A.TRUE
  2. B.FALSE
Q75
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Bus Architecture (Bidirectional Data Bus)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Why is the system data bus classified as bidirectional?
  1. A.To way
  2. B.Data moves from both, processor to memory and memory to processor
  3. C.Data moves from both, processor to memory and memory to data Bus
  4. D.None of the Given
Q76
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Bus Architecture (Control Bus Characteristics)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In system bus architecture, the control bus carries control and status signals (such as Read/Write, Interrupt Acknowledge, and Clock) and is __________ in nature.
  1. A.is Not Important
  2. B.is Important
  3. C.bidirectional
  4. D.unidirectional
Q77
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Bus Architecture (Byte Definition 8 Bits)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
A standard byte-addressable memory cell is an $n$-bit storage location containing how many bits?
  1. A.4-bit
  2. B.8-bit
  3. C.6-bit
  4. D.80-bit
Q78
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Bus Architecture (Memory Dimensions: Cell Width and Cell Count)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The number of bits in a single memory cell is called the cell width. Which two parameters completely define a memory unit?
  1. A.Cell width and number of cells
  2. B.Cell number and width of the cells
  3. C.Width and height
  4. D.Height and total size
Q79
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Bus Architecture (Parallel Bits per Memory Cell)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When defining the two dimensions of memory, what does the first dimension specify?
  1. A.How many parallel bits are there in a single memory cell
  2. B.How many vertical cells exist in memory
  3. C.The physical long dimension of the RAM chip
  4. D.The short bus latency
Q80
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Bus Architecture (Data Bus and Cell Width Alignment)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which memory access operation architecture is considered the best and simplest?
  1. A.Normal operation
  2. B.Best and simplest operation (matching data bus width and cell width)
  3. C.First operation
  4. D.None of the Given