Ch 05: Subroutines and Stack Architecture

222 Questions222 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
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Showing 191 โ€“ 200 of 222 Questions
Page 20 of 23
Q191
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 8-Bit DIV Instruction Implicit Dividend (AX)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a 16-bit dividend is divided by an 8-bit divisor using the DIV instruction, the dividend must be loaded into register:
๐Ÿ’ป assembly Snippet
div bl
  1. A.AX
  2. B.BX
  3. C.CX
  4. D.DX
Q192
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 16-Bit DIV Instruction Quotient Bit WidthEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a 32-bit dividend in DX:AX is divided by a 16-bit divisor, the resulting quotient is of what size?
๐Ÿ’ป assembly Snippet
div bx
  1. A.32 bits
  2. B.16 bits
  3. C.8 bits
  4. D.4 bits
Q193
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 8-Bit DIV Instruction Quotient Destination (AL)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a 16-bit dividend in AX is divided by an 8-bit divisor, the resulting 8-bit quotient will be stored in register:
๐Ÿ’ป assembly Snippet
div bl
  1. A.AX
  2. B.AL
  3. C.AH
  4. D.DX
Q194
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 16-Bit DIV Instruction Implicit Dividend WidthEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the operand of a DIV instruction is 16 bits wide, how many bits wide is the implicit dividend stored in DX:AX?
๐Ÿ’ป assembly Snippet
div bx
  1. A.64-bit
  2. B.32-bits
  3. C.16-bits
  4. D.8-bits
Q195
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ DIV Instruction 8-Bit and 16-Bit FormsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In 8088 microprocessor architecture, how many forms does the DIV instruction have?
๐Ÿ’ป assembly Snippet
div bl  ; 8-bit form
div bx  ; 16-bit form
  1. A.Two forms
  2. B.Three forms
  3. C.Four forms
  4. D.One form
Q196
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 16-Bit DIV Instruction Implicit Dividend WidthEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the operand of a DIV instruction is 16 bits wide, how many bits wide is the implicit dividend stored in register pair DX:AX?
๐Ÿ’ป assembly Snippet
div bx
  1. A.8 bits
  2. B.16 bits
  3. C.32 bits
  4. D.64 bits
Q197
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 5.2. Parameter PassingEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is the maximum number of parameters a subroutine can receive via registers in 8088 architecture when all general-purpose registers are utilized?
  1. A.6
  2. B.7
  3. C.5
  4. D.4
Q198
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 5.1. Subroutine MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
To transfer control back to the caller from a subroutine, how many explicit operands does the standard RET instruction require?
๐Ÿ’ป assembly Snippet
ret
  1. A.1 argument
  2. B.2 arguments
  3. C.3 arguments
  4. D.No arguments
Q199
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 5.2. Parameter PassingEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is the maximum number of parameter arguments a subroutine can receive using CPU general-purpose registers in 8088 architecture?
  1. A.6
  2. B.7
  3. C.8
  4. D.9
Q200
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 5.1. Subroutine MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
After executing a standard 16-bit 'RET' instruction to return from a subroutine, how is the Stack Pointer (SP) updated?
๐Ÿ’ป assembly Snippet
ret
  1. A.SP is incremented by 2
  2. B.SP is decremented by 2
  3. C.SP is incremented by 1
  4. D.SP is decremented by 1