Ch 05: Subroutines and Stack Architecture

222 Questions222 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 181 โ€“ 190 of 222 Questions
Page 19 of 23
Q181
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ Binary Multiplication via Left Bit ShiftingEasyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
To multiply an unsigned binary number stored in a register by 2, which operation should be performed on the register?
๐Ÿ’ป assembly Snippet
shl ax, 1
  1. A.Shifted left by one bit (SHL/SAL)
  2. B.Shifted right by one bit (SHR)
  3. C.Rotated right by one bit (ROR)
  4. D.Incremented by two
Q182
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 16-Bit DIV Implied 32-Bit DividendEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the operand of a DIV instruction is 16 bits wide, the implied dividend stored in register pair DX:AX is:
๐Ÿ’ป assembly Snippet
div bx
  1. A.8 bits
  2. B.16 bits
  3. C.32 bits
  4. D.64 bits
Q183
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ DIV Instruction Operand Forms (8-Bit and 16-Bit)Easyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In 8088 assembly language, the DIV (Unsigned Division) instruction has how many fundamental operand size forms?
๐Ÿ’ป assembly Snippet
div bl
div bx
  1. A.Two forms
  2. B.Three forms
  3. C.Four forms
  4. D.Five forms
Q184
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ Divide Overflow Exception (Interrupt 0)Mediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a dividend is divided by a small divisor such that the resulting quotient exceeds the storage capacity of the destination register, what error is triggered?
๐Ÿ’ป assembly Snippet
mov ax, 10000
mov bl, 2
div bl
  1. A.Divide logical error
  2. B.Divide overflow error
  3. C.Divide syntax error
  4. D.An illegal instruction
Q185
๐Ÿง  Long Problem๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ Extended Shifting Chaining Mechanics (SHL and RCL)Mediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain how extended shifting (32-bit/multi-word bit shifting) is performed in 16-bit 8088 assembly language using shift and rotate instructions.
๐Ÿ’ป assembly Snippet
num1: dd 40000

; Perform 32-bit Left Shift by 1 bit:
shl word [num1], 1      ; Shift lower 16 bits left; MSB enters Carry Flag
rcl word [num1+2], 1    ; Rotate upper 16 bits left through Carry Flag
Q186
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ MUL Instruction Unsigned MultiplicationEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which instruction performs an unsigned multiplication of a source operand with the accumulator register?
๐Ÿ’ป assembly Snippet
mul bx
  1. A.MULTI
  2. B.DIV
  3. C.MUL
  4. D.MOVE
Q187
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ Unsigned Division via DIV InstructionEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which assembly instruction is used to perform unsigned integer division in 8088 CPU architecture?
๐Ÿ’ป assembly Snippet
div bx
  1. A.DIV instruction
  2. B.ADC instruction
  3. C.SBB instruction
  4. D.DIVI instruction
Q188
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 16-Bit DIV Instruction Quotient Bit WidthEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a 32-bit dividend in DX:AX is divided by a 16-bit operand using the DIV instruction, the resulting quotient is how many bits wide?
๐Ÿ’ป assembly Snippet
div bx
  1. A.32 bits
  2. B.16 bits
  3. C.8 bits
  4. D.4 bits
Q189
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 16-Bit DIV Instruction Quotient Bit WidthEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a 32-bit dividend in register pair DX:AX is divided by a 16-bit divisor using the DIV instruction, the resulting quotient is how many bits wide?
๐Ÿ’ป assembly Snippet
div bx
  1. A.32 bits
  2. B.16 bits
  3. C.8 bits
  4. D.4 bits
Q190
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 5๐Ÿท๏ธ 16-Bit DIV Instruction Dividend PlacementEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the operand of the DIV instruction is 16 bits wide, where is the implied 32-bit dividend stored?
๐Ÿ’ป assembly Snippet
div bx
  1. A.AX register alone
  2. B.The concatenation of DX and AX (DX:AX)
  3. C.The concatenation of ES and AX
  4. D.The concatenation of DS and BX