← CS401 - Computer Architecture and Assembly Language Programming OverviewChapter 8

Ch 08: String Instructions and Primitives

307 Questions307 MCQs0 Short Questions0 Long Questions
🎯 Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

📘 VU MID TERM EXAMLectures 1 to 22
⏱️ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

📝30 MCQs
⏱️60 Minutes
Starter (1 Attempt)1 Attempt
PKR 10
Standard (2 Attempts)2 Attempts
PKR 20Most Popular
Mastery (5 Attempts)5 Attempts
PKR 50Best Value
📘 Take VU Mid Term Exam
📗 VU FINAL TERM EXAMLectures 23 to 45
⏱️ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

📝45 MCQs
⏱️90 Minutes
Starter (1 Attempt)1 Attempt
PKR 10
Standard (2 Attempts)2 Attempts
PKR 20Most Popular
Mastery (5 Attempts)5 Attempts
PKR 50Best Value
📗 Take VU Final Term Exam
Showing 61 – 70 of 307 Questions
Page 7 of 31
Q61
❓ MCQ📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (IRQ Conflict Condition)Easy🔁⭐💡📄🎓VU🏛️VU
When two distinct hardware expansion devices attempt to utilize the same Interrupt Request (IRQ) line simultaneously, what condition occurs?
  1. A.An IRQ Collision
  2. B.An IRQ Conflict
  3. C.An IRQ Crash
  4. D.An IRQ Blockage
Q62
🧠 Long Problem📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (Breakpoint Interrupt Service Routine INT 3 ISR)Hard⭐💡📄🎓VU🏛️VU
Write a complete x86 assembly Breakpoint Interrupt Service Routine (ISR for `INT 3`) that preserves all general-purpose and segment registers on the stack and sets up a stack frame to inspect register states upon hitting a breakpoint.
💻 assembly Snippet
debugISR:
    push bp
    mov bp, sp
    push ax
    push bx
    push cx
    push dx
    push si
    push di
    push ds
    push es
    sti
    ; Debugger processing...
    pop es
    pop ds
    pop di
    pop si
    pop dx
    pop cx
    pop bx
    pop ax
    pop bp
    iret
Q63
🧠 Long Problem📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (Breakpoint/Trap ISR Handler and IVT Hooking)Hard⭐💡📄🎓VU🏛️VU
Write the complete x86 assembly language implementation of a Breakpoint and Single-Step Trap Interrupt Service Routine (`trapisr` for `INT 1` / `INT 3`) along with the main program instructions to hook the handler vector into the Interrupt Vector Table (IVT).
💻 assembly Snippet
; --- Single-Step / Breakpoint ISR Hooking Setup ---
start:
    xor ax, ax
    mov es, ax                  ; ES = 0000h (IVT Base)
    mov word [es:1*4], trapisr   ; Store vector 1 offset
    mov word [es:1*4+2], cs      ; Store vector 1 segment
Q64
📝 Short Q📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (IVT Vector Hooking for INT 3 and INT 9)Medium⭐💡📄🎓VU🏛️VU
Write the x86 assembly language instructions to hook the Breakpoint Interrupt (`INT 3`) and Keyboard Interrupt (`INT 9`) vectors into the Interrupt Vector Table (IVT) using critical section protection (`CLI`/`STI`).
💻 assembly Snippet
mov word [es:3*4], debugisr ; INT 3 vector offset
mov word [es:3*4+2], cs    ; INT 3 vector segment
cli
mov word [es:9*4], kbisr   ; INT 9 vector offset
mov word [es:9*4+2], cs    ; INT 9 vector segment
sti
Q65
❓ MCQ📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (INT 2 Non-Maskable Interrupt NMI)Easy🔁⭐💡📄🎓VU🏛️VU
Which of the following processor interrupts is classified as a Non-Maskable Interrupt (NMI) that cannot be disabled using the `CLI` instruction?
  1. A.INT 2
  2. B.INT 3
  3. C.INT 0
  4. D.INT 1
Q66
❓ MCQ📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (IRQ 3 Serial Port COM 2 Assignment)Easy🔁⭐💡📄🎓VU🏛️VU
In IBM PC hardware architecture, which Interrupt Request line (IRQ) is connected to serial communications port COM 2?
  1. A.IRQ 0
  2. B.IRQ 1
  3. C.IRQ 2
  4. D.IRQ 3
Q67
❓ MCQ📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (System Timer Tick 55ms Interval)Easy🔁⭐💡📄🎓VU🏛️VU
In standard IBM PC hardware architecture, what is the default time interval between two consecutive system timer tick interrupts (IRQ 0 / INT 8)?
  1. A.40ms
  2. B.45ms
  3. C.50ms
  4. D.55ms
Q68
❓ MCQ📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (INT 1 Single Step Exception Mechanics)Easy🔁⭐💡📄🎓VU🏛️VU
In x86 processor exception architecture, the Single Step / Trap interrupt (`INT 1`) is classified as an internal CPU hardware exception __________.
  1. A.Hardware interrupt
  2. B.Like divide by zero interrupt
  3. C.Like divide by 1 interrupt
  4. D.Software interrupt
Q69
❓ MCQ📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (IRQ 0 Programmable Interval Timer Interrupt)Easy🔁⭐💡📄🎓VU🏛️VU
In standard IBM PC hardware architecture, which Interrupt Request line (IRQ) is driven by the Programmable Interval Timer (PIT) hardware chip?
  1. A.IRQ 0
  2. B.IRQ 1
  3. C.IRQ 2
  4. D.IRQ 3
Q70
❓ MCQ📘 CS401📑 Lec 8🏷️ 8.1. Hardware Interrupts (8259A PIC Port 0x20 Command Register)Easy🔁⭐💡📄🎓VU🏛️VU
In the 8259A Programmable Interrupt Controller (PIC), which I/O port address serves as the Command / Control port for the master PIC?
💻 assembly Snippet
mov al, 0x20 ; Non-specific End of Interrupt (EOI) command
out 0x20, al ; Send EOI command to Master PIC Control Port 0x20
  1. A.19
  2. B.20
  3. C.21
  4. D.22

📖 Related CS401 - Computer Architecture and Assembly Language Programming Curriculum Units

Continue practicing topic-wise multiple choice questions from adjacent examination units.

View All CS401 - Computer Architecture and Assembly Language Programming Chapters →
Ch 01: Introduction to Assembly Language387 QsCh 02: 16-Bit Segmented Memory Model & Addressing Modes395 QsCh 03: Branching, Loops and Program Flow261 QsCh 04: Bit Manipulation and Shifts198 QsCh 05: Subroutines and Stack Architecture222 QsCh 06: Parameter Passing and Stack Frames216 Qs