Ch 01: Introduction to Assembly Language

387 Questions387 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 191 โ€“ 200 of 387 Questions
Page 20 of 39
Q191
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Three-Bus System ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What are the three fundamental system buses used by the CPU to communicate with memory and peripheral devices?
  1. A.Address, Line, and Data buses
  2. B.Address, Control, and Line buses
  3. C.Address, Control, and Data buses
  4. D.None of the given options
Q192
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Unidirectional Address Bus CharacteristicsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: The address bus is strictly unidirectional, carrying physical memory location signals exclusively from the processor to memory and I/O devices.
  1. A.True
  2. B.False
Q193
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Bidirectional Data Bus MechanicsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The system Data Bus is bidirectional because:
  1. A.It carries 2-way traffic only
  2. B.Data moves in both directions: from processor to memory (write) and memory to processor (read)
  3. C.Data moves from processor to memory and data bus
  4. D.None of the given options
Q194
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Control Bus Signal DirectionalityEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
As a collection of individual timing and command lines, the system Control Bus is classified as:
  1. A.One way
  2. B.Unidirectional
  3. C.Bidirectional
  4. D.None of the given options
Q195
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 8-Bit Byte Memory Cell Storage UnitEasyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
A standard byte memory cell is an ________ location used to store data in system memory.
  1. A.4-bit
  2. B.8-bit
  3. C.16-bit
  4. D.32-bit
Q196
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Memory System Definition ParametersEasyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The total size and organization of a computer memory system are completely defined by which two parameters?
  1. A.Cell width and total number of cells
  2. B.Cell number and cell height
  3. C.Width and segment count
  4. D.Bus width and line count
Q197
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Memory Dimensions (Cell Width vs Depth)Easyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When defining memory dimensions, the first dimension specifies how many bits exist in a single memory cell, forming the ________ dimension.
  1. A.Parallel (Cell Width)
  2. B.Vertical (Total Cells)
  3. C.Longitudinal
  4. D.Short
Q198
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Memory Cell Width vs Data Bus ConstraintsEasyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: In standard hardware architecture design, an individual memory cell cannot be wider than the width of the system data bus.
  1. A.True
  2. B.False
Q199
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Control Bus Read/Write SignalingEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which system bus carries command signals expressing the intent of the processor to perform either a read or write operation?
  1. A.Control bus
  2. B.Address bus
  3. C.Data bus
  4. D.Both control and data
Q200
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ Processor Role in Bus Control SignalingEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Transmitting appropriate control signals on the control bus to coordinate memory read/write timing is the responsibility of the:
  1. A.Control Bus
  2. B.Peripherals
  3. C.Processor (Control Unit)
  4. D.Memory