Ch 01: Introduction to Assembly Language

387 Questions387 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 11 โ€“ 20 of 387 Questions
Page 2 of 39
Q11
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Processor Registers and Instruction PointerEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The Instruction Pointer (IP) register holds the memory address of the ________.
  1. A.Next instruction to be executed
  2. B.Previous instruction to be executed
  3. C.Current instruction
  4. D.None of the given
Q12
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Processor Registers and Flags RegisterEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which register contains individual bits that each specify a distinct condition, status, or control code (such as Carry, Zero, Sign, Overflow)?
  1. A.Flag register
  2. B.Accumulator Register
  3. C.Pointer Register
  4. D.Index register
Q13
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Processor RegistersEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Registers are specialized high-speed storage cells located ________.
  1. A.Inside the processor
  2. B.Outside the processor
  3. C.Both inside and outside the processor
  4. D.None of the given
Q14
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Assembly LanguageEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Assembly language is NOT a low-level language. (True/False)
  1. A.False
  2. B.True
Q15
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Buses (Address, Data, Control)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which system bus is used by the processor to inform memory or I/O devices which specific location to read from or write to?
  1. A.Address bus
  2. B.Control bus
  3. C.Data bus
  4. D.RAM
Q16
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Memory Organization and Byte Ordering (Little-Endian)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Intel x86 processor architectures follow which byte-ordering convention in memory storage?
  1. A.Littel endian
  2. B.Big endian
  3. C.Both littel endian and big endian
  4. D.None of the given
Q17
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Evolution of MicroprocessorsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The first 16-bit processor produced by Intel was the 8085 processor. (True/False)
  1. A.False
  2. B.True
Q18
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Processor Registers ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
CPU registers are also referred to as scratchpad RAM. (True/False)
  1. A.True
  2. B.False
Q19
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Processor RegistersEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is the primary function of a CPU register in assembly language operations?
  1. A.Hold the operand
  2. B.Hold the operator
  3. C.Hold both the operator and operand
  4. D.None of the given
Q20
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. System Buses (Address, Data, Control)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which system bus is used by the processor to specify the memory location or I/O device to read from or write to?
  1. A.Address bus
  2. B.Control bus
  3. C.Data bus
  4. D.RAM