Ch 03: Branching, Loops and Program Flow

261 Questions261 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 61 โ€“ 70 of 261 Questions
Page 7 of 27
Q61
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (MUL Unsigned Multiplication)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which x86 assembly instruction performs an unsigned multiplication of the source operand and the accumulator register?
๐Ÿ’ป assembly Snippet
mov ax, 25
mov bx, 4
mul bx ; AX * BX -> Product in DX:AX (0x0000:0x0064)
  1. A.Multi
  2. B.DIV
  3. C.MUL
  4. D.Move
Q62
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (Little-Endian Machine Instruction Encoding)Medium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
If `BB` is the opcode for moving a 16-bit constant to register `BX` (or `B8` for `AX`), and decimal constant 336 equals hex `0x0150`, what is the hexadecimal representation of the instruction `MOV AX, 336` (`0x0150`) using x86 Little-Endian byte ordering (where opcode is `BB` as specified in question prompt)?
๐Ÿ’ป assembly Snippet
; Instruction: MOV AX, 0x0150
; Opcode = BB, Immediate = 0x0150 (Low byte = 50, High byte = 01)
; Machine encoding bytes: BB 50 01 -> 0xBB5001
  1. A.0xBB0150
  2. B.0x5001BB
  3. C.0x01BB50
  4. D.0xBB5001
Q63
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (Instruction Operand Counting)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In the assembly instruction `MOV AX, 5`, how many operands are present?
๐Ÿ’ป assembly Snippet
mov ax, 5 ; 2 operands: AX (destination), 5 (source)
  1. A.1
  2. B.2
  3. C.3
  4. D.4
Q64
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Register Architecture (CX Count Register)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In assembly language, the CX register is normally used as a __________ register.
๐Ÿ’ป assembly Snippet
mov cx, 10 ; Load iteration count 10 into CX
  1. A.source
  2. B.counter
  3. C.index
  4. D.pointer
Q65
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (8-Bit DIV Dividend Register AX)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a 16-bit dividend is divided by an 8-bit divisor (`DIV reg8`), which register must hold the 16-bit dividend prior to division?
๐Ÿ’ป assembly Snippet
mov ax, 200 ; 16-bit dividend in AX
mov bl, 10  ; 8-bit divisor in BL
div bl      ; AL = 20 (Quotient), AH = 0 (Remainder)
  1. A.AX
  2. B.BX
  3. C.CX
  4. D.DX
Q66
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Register Architecture (Index Registers SI and DI Function)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In x86 assembly language architecture, what primary data type do Index Registers (such as `SI` and `DI`) store during memory access?
๐Ÿ’ป assembly Snippet
mov si, offset_data ; SI holds memory address offset
  1. A.Address
  2. B.Data
  3. C.Intermediate result
  4. D.Both data and addresses
Q67
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Register Architecture (FLAGS Register Bit Significance)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In which processor register do the individual bits work independently and bit-wise individually to hold distinct status flags or control states?
  1. A.flags register
  2. B.index register
  3. C.base register
  4. D.accumulator
Q68
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (16-Bit DIV Quotient Width)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a 32-bit dividend stored in register pair DX:AX is divided by a 16-bit divisor operand using `DIV`, what is the bit width of the resulting quotient stored in AX?
๐Ÿ’ป assembly Snippet
div cx ; Quotient (16-bit) stored in AX, Remainder (16-bit) stored in DX
  1. A.4 bits
  2. B.32 bits
  3. C.16 bits
  4. D.8 bits
Q69
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (8-Bit DIV Quotient Register AL)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a 16-bit dividend in AX is divided by an 8-bit divisor operand using `DIV`, in which register is the quotient placed?
๐Ÿ’ป assembly Snippet
div bl ; Quotient stored in AL, Remainder stored in AH
  1. A.AL
  2. B.AX
  3. C.AH
  4. D.DX
Q70
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (ADC Operand Count)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
How many explicit operands does the Add with Carry instruction `ADC` take in assembly language syntax?
๐Ÿ’ป assembly Snippet
adc ax, bx ; 2 explicit operands: AX (destination) and BX (source)
  1. A.3
  2. B.0
  3. C.1
  4. D.2