Ch 03: Branching, Loops and Program Flow

261 Questions261 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 51 โ€“ 60 of 261 Questions
Page 6 of 27
Q51
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Register Architecture (Index Registers SI and DI)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which registers serve as the primary Index Registers in x86 Intel architecture to hold memory addresses for string and block memory access?
๐Ÿ’ป assembly Snippet
mov si, src_buffer
mov di, dest_buffer
rep movsb ; Uses SI and DI as source and destination index pointers
  1. A.SI and SS
  2. B.PI and DI
  3. C.SI and IP
  4. D.SI and DI
Q52
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Register Architecture (FLAGS Register Bit Layout)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which processor register is bit-wise significant, meaning each individual bit position has a distinct status or control meaning?
  1. A.AX
  2. B.FS
  3. C.IP
  4. D.Flags Register
Q53
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (Carry Flag Addition Overflow)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When two 16-bit numbers are added, the sum can be 17 bits long. Where is this extra 17th carry bit placed so it can be subsequently tested?
๐Ÿ’ป assembly Snippet
add ax, bx ; 17th bit stored in Carry Flag (CF)
  1. A.carry flag
  2. B.Parity Flag
  3. C.Auxiliary Carry
  4. D.Zero Flag
Q54
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (Intel Syntax Operand Order)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: In Intel x86 assembly language syntax, instructions are formatted as `operation destination, source`.
๐Ÿ’ป assembly Snippet
mov ax, bx ; Destination = AX, Source = BX
  1. A.TRUE
  2. B.FALSE
Q55
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (ADD Instruction Action)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Executing the assembly operation `add ax, bx` performs which action?
๐Ÿ’ป assembly Snippet
add ax, bx ; AX = AX + BX (BX remains unchanged)
  1. A.Add the bx to ax and change the bx
  2. B.Add the ax to bx and change the ax
  3. C.Add the bx to ax and change the ax
  4. D.Add the bx to ax and change nothing
Q56
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (Define Byte DB Directive)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In assembly language, allocating data using the Define Byte directive (e.g., `num1: db 0`) reserves how much memory space?
๐Ÿ’ป assembly Snippet
num1: db 0 ; Allocates 1 byte of memory
  1. A.1byte
  2. B.4bit
  3. C.16bit
  4. D.2byte
Q57
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (ADD AX, BX Accumulation Comment)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Consider the following assembly code snippet: ```assembly [org 0x0100] mov ax, [num1] ; load first number in ax mov bx, [num2] ; load second number in bx add ax, bx ; _________________________________ int 0x21 num1: dw 5 num2: dw 10 ``` What is the most appropriate code comment for line 4 (`add ax, bx`)?
๐Ÿ’ป assembly Snippet
add ax, bx ; accumulate sum in ax
  1. A.No comments Will be
  2. B.; accumulate sum in add
  3. C.; accumulate sum in ax
  4. D.; accumulate sum in Bx
Q58
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (16-Bit Unsigned Division DIV DX:AX)Medium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The 16-bit unsigned division instruction `DIV operand` divides a 32-bit dividend stored in register pair `DX:AX` by its 16-bit operand. Where are the quotient and remainder stored upon completion?
๐Ÿ’ป assembly Snippet
mov dx, 0
mov ax, 100
mov cx, 7
div cx ; AX = 14 (Quotient), DX = 2 (Remainder)
  1. A.Quotient in AX, Remainder in DX
  2. B.Quotient in DX, Remainder in AX
  3. C.Quotient in AL, Remainder in AH
  4. D.Quotient in CX, Remainder in BX
Q59
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (DIV 16-Bit Quotient Storage in AX)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The 16-bit unsigned division instruction `DIV` divides a 32-bit dividend stored in register pair `DX:AX` by a 16-bit divisor operand and stores the __________ quotient in register `AX`.
๐Ÿ’ป assembly Snippet
mov dx, 0
mov ax, 500
mov cx, 10
div cx ; 16-bit quotient (50) is stored in AX
  1. A.16bit
  2. B.17bit
  3. C.32bit
  4. D.64bit
Q60
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (DIV Integer Division)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which x86 assembly language instruction is used to perform integer division (as opposed to floating-point division)?
  1. A.DIV instruction
  2. B.ADC instruction
  3. C.SBB instruction
  4. D.DIVI instruction