Ch 04: Bit Manipulation and Shifts

198 Questions198 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 21 โ€“ 30 of 198 Questions
Page 3 of 20
Q21
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.2. Multiplication and Division InstructionsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
For the execution of the instruction `DIV BL`, in which register is the implied dividend stored?
๐Ÿ’ป assembly Snippet
DIV BL
  1. A.AX
  2. B.BX
  3. C.CX
  4. D.DX
Q22
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Shift and Rotate Instructions (RCR and RCL)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In a Rotate Through Carry Right (RCR) instruction executed on a 16-bit word operand, the rotation effectively operates across a total ring of how many bits?
๐Ÿ’ป assembly Snippet
RCR AX, 1
  1. A.17 bits rotation
  2. B.16 bits rotation
  3. C.1 bit rotation
  4. D.8 bits rotation
Q23
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Shift Instructions and Bitwise ArithmeticEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Suppose the decimal number 35 is shifted right by one bit position using a logical right shift instruction (`SHR`). What will be the resulting decimal value?
๐Ÿ’ป assembly Snippet
MOV AL, 35
SHR AL, 1
  1. A.17
  2. B.35
  3. C.70
  4. D.140
Q24
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.2. Shifting and RotationsEasyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
If register D contains decimal 35, what is the new value after performing a bitwise logical shift left by 2 bits (`35 << 2`)?
๐Ÿ’ป assembly Snippet
mov ax, 35
shl ax, 2 ; AX = 35 * 4 = 140
  1. A.35
  2. B.70
  3. C.140
  4. D.17
Q25
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.5. Bitwise Logical OperationsMediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain the purpose, mechanics, and usage of the `TEST` instruction in x86 assembly language.
๐Ÿ’ป assembly Snippet
test ax, 0x0001 ; Tests if Bit 0 is set without changing AX
Q26
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Addressing Modes (Immediate Label vs Memory Contents Addressing)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
If variable `Num1` is located at memory offset address `0x0117` and stores the data value `0x0005`, what value will register `BX` contain after executing `mov bx, Num1` in NASM assembly?
๐Ÿ’ป assembly Snippet
mov bx, Num1   ; BX = 0x0117 (immediate address offset)
mov bx, [Num1] ; BX = 0x0005 (memory contents)
  1. A.0005
  2. B.0117
  3. C.Num1
  4. D.1701
Q27
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Assembly Syntax Errors (Size Mismatch and Directives)Mediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain common assembly language program syntax and semantic errors, such as 'Size Mismatch Error', and how to correct them.
๐Ÿ’ป assembly Snippet
mov ax, bl       ; ERROR: Size mismatch (16-bit vs 8-bit)
mov byte [bx], 5 ; CORRECT: Explicit size directive
Q28
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Assembly Syntax Errors (Size Mismatch Syntax Error)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: A 'Size Mismatch Error' in assembly language programming is classified as a compile-time syntax error.
  1. A.False
  2. B.True
Q29
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Segmented Memory Model (CS:IP Default Pairing)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
By default, the Code Segment register (CS) is implicitly paired with which register to form full instruction addresses (CS:IP)?
  1. A.SS
  2. B.BP
  3. C.CX
  4. D.IP
Q30
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Addressing Modes (Memory-to-Memory Limitation)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
True or False: In x86 assembly language architecture, direct memory-to-memory operations (such as `mov [mem1], [mem2]`) are directly supported in a single instruction.
๐Ÿ’ป assembly Snippet
; ILLEGAL: mov [mem1], [mem2]
; LEGAL:
mov ax, [mem2]
mov [mem1], ax
  1. A.True
  2. B.False