Ch 04: Bit Manipulation and Shifts

198 Questions198 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

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๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
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Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

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๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
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Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
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Showing 11 โ€“ 20 of 198 Questions
Page 2 of 20
Q11
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Shift Instructions (SHR vs SAR/SHL)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which shift operation inserts a zero from the left (MSB), moves every bit one position to the right, and copies the rightmost bit (LSB) into the Carry Flag?
๐Ÿ’ป assembly Snippet
SHR AL, 1
  1. A.None of the given
  2. B.SHL
  3. C.SAL
  4. D.SAR
Q12
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Bit Manipulation and Shift InstructionsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which rotation instruction inserts the Carry Flag into the left (MSB), moves every bit one position to the right, and drops the rightmost bit (LSB) into the Carry Flag?
๐Ÿ’ป assembly Snippet
RCR AL, 1
  1. A.RCR
  2. B.ROL
  3. C.RCL
  4. D.ROR
Q13
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Shift Instructions (SHL vs SAL)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The SHL (Shift Logical Left) and SAL (Shift Arithmetic Left) assembly instructions perform identical binary bit operations. (True/False)
๐Ÿ’ป assembly Snippet
SHL AL, 1
SAL AL, 1
  1. A.True
  2. B.False
Q14
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Shift Instructions (SHL and SAL)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which shift operation inserts a zero bit from the right (LSB), moves every bit one position to its left, and drops the most significant bit (MSB) into the Carry Flag?
๐Ÿ’ป assembly Snippet
SHL AL, 1
SAL AL, 1
  1. A.both shl and sal
  2. B.shl
  3. C.sal
  4. D.sar
Q15
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Bitwise Logical Instructions (XOR)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In a bitwise XOR (Exclusive OR) logical operation, the output bit is 1 under which condition?
๐Ÿ’ป assembly Snippet
XOR AL, BL
  1. A.both inputs are different
  2. B.both inputs are same
  3. C.I and II
  4. D.none of the above
Q16
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Bitwise Logical Instructions (AND)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In a bitwise AND logical operation, the output bit is 1 under which condition?
๐Ÿ’ป assembly Snippet
AND AL, BL
  1. A.Both inputs are 1
  2. B.Both inputs are 0
  3. C.One is 0 and other is 1
  4. D.None of the given
Q17
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.2. Multiplication and Division InstructionsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the divisor operand of a DIV instruction is 16-bits (a word), where is the implied dividend stored?
๐Ÿ’ป assembly Snippet
DIV CX
  1. A.The concatenation of DX and AX
  2. B.AX register
  3. C.The concatenation of ES and AX
  4. D.The concatenation of DS and BX
Q18
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.2. Multiplication and Division InstructionsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the divisor operand of a DIV instruction is 16 bits, what is the bit size of the implied dividend stored in DX:AX?
๐Ÿ’ป assembly Snippet
DIV BX
  1. A.32 bit
  2. B.16 bit
  3. C.64 bit
  4. D.8 bit
Q19
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.1. Shift Instructions and Bitwise ArithmeticEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Suppose the AL register contains the decimal value 5. After executing two bitwise left shift (SHL) operations, what value will AL hold?
๐Ÿ’ป assembly Snippet
MOV AL, 5
SHL AL, 1
SHL AL, 1
  1. A.20
  2. B.5
  3. C.10
  4. D.15
Q20
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ 4.2. Multiplication and Division InstructionsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
For the execution of the 8-bit division instruction `DIV BL`, in which register is the implied dividend stored?
๐Ÿ’ป assembly Snippet
DIV BL
  1. A.AX
  2. B.BX
  3. C.CX
  4. D.DX