Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

395 Questions395 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
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Showing 381 โ€“ 390 of 395 Questions
Page 39 of 40
Q381
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.2. Data Definition DirectivesEasyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
How does an assembler handle code labels compared to data labels, and what responsibility falls on the programmer regarding their use?
๐Ÿ’ป assembly Snippet
; Code vs Data Labels
data_var: dw 100    ; Data label marking variable address

code_start:         ; Code label marking jump target
mov ax, [data_var]
jmp code_start
Q382
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.3. Addressing ModesMediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Differentiate between Based Addressing and Indexed Addressing in 8086 register indirect memory access.
๐Ÿ’ป assembly Snippet
; Based vs Indexed Addressing Examples
mov ax, [bx]  ; Based Addressing using BX
mov ax, [si]  ; Indexed Addressing using SI
Q383
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.3. Addressing ModesMediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain Register + Offset Addressing (Base + Offset and Index + Offset) in 8086 assembly language with code examples.
๐Ÿ’ป assembly Snippet
; Register + Offset Addressing Examples
mov ax, [bx + 4]   ; Base + Offset (BX + constant displacement)
mov cx, [si + 2]   ; Index + Offset (SI + constant displacement)
mov dx, [bp + 6]   ; Base + Offset accessing stack frame parameter
Q384
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Segment RegistersMediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is an Effective Address (EA) in 8086 memory addressing, and why is an EA meaningless without segment association?
๐Ÿ’ป assembly Snippet
; Segment Association with Effective Address
mov ax, [bx + 4]  ; EA = BX + 4 (Offset relative to Data Segment DS)
; Physical Address = (DS * 16) + EA
Q385
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Segment RegistersMediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What are default segment register associations in 8086 architecture, which register pairs are permanently locked, and which can be overridden?
๐Ÿ’ป assembly Snippet
; Default Segment Associations Example
mov ax, [bx]    ; Uses DS:BX by default
mov ax, [bp]    ; Uses SS:BP by default
Q386
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Segment RegistersMediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is a Segment Override Prefix in 8086 assembly language, and how does it temporarily alter default segment associations?
๐Ÿ’ป assembly Snippet
; Segment Override Prefix Example
mov ax, [bx]       ; Reads from Data Segment (DS:BX)
mov ax, [cs:bx]    ; Overrides default: reads from Code Segment (CS:BX)
mov ax, [bx]       ; Reverts to default Data Segment (DS:BX)
Q387
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Segment RegistersHardโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain Segment Wraparound and Physical Address Wraparound in 8086 memory architecture.
๐Ÿ’ป assembly Snippet
; Segment Wraparound Example
mov bx, 0xFFFF
mov ax, [bx + 2]   ; EA = 0xFFFF + 2 = 0x10001 -> Wraps to offset 0x0001 in DS
Q388
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Segment RegistersHardโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Calculate the effective address and physical address for the following scenarios in 8086 architecture, demonstrating both Segment-Level Wraparound and Physical Address Wraparound: 1. BX = 0x9100, DS = 0x1500, with memory access [BX + 0x7000]. 2. BX = 0x0100, DS = 0xFFF0, with memory access [BX + 0x0100].
๐Ÿ’ป assembly Snippet
; Segment and Physical Wraparound Examples
mov bx, 0x9100
mov ax, [bx + 0x7000] ; EA wraps to 0x0100 within segment

mov ax, 0xFFF0
mov ds, ax
mov bx, 0x0100
mov cx, [bx + 0x0100] ; Physical address wraps to 0x00100 in RAM
Q389
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.3. Addressing ModesMediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Distinguish between Operand Types and Memory Addressing Modes in iAPX88 (8088) architecture, and explain the general formula 'Base + Index + Offset'.
๐Ÿ’ป assembly Snippet
; General Memory Addressing Formula: [Base + Index + Offset]
mov ax, [bx + si + 4]  ; Base (BX) + Index (SI) + Constant Offset (4)
Q390
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.3. Addressing ModesEasyโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain Direct Addressing and Based Register Indirect Addressing modes in 8086 assembly language, illustrating how destination register size dictates memory write length.
๐Ÿ’ป assembly Snippet
; Direct vs Based Register Indirect Addressing
mov [1234], ax  ; Direct Addressing: writes 16-bit word to offset 1234
mov [1234], al  ; Direct Addressing: writes 8-bit byte to offset 1234
mov bx, 0x1234
mov cx, [bx]    ; Based Register Indirect Addressing via BX