Ch 02: 16-Bit Segmented Memory Model & Addressing Modes

395 Questions395 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 11 โ€“ 20 of 395 Questions
Page 2 of 40
Q11
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.4. Memory AddressingEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
By default, the Base Pointer (BP) register is associated with which segment register during physical memory address calculation?
๐Ÿ’ป assembly Snippet
mov ax, [bp]
  1. A.SS (Stack Segment)
  2. B.DS (Data Segment)
  3. C.CS (Code Segment)
  4. D.ES (Extra Segment)
Q12
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.4. Memory AddressingEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In direct addressing mode, the memory address (offset) specified within the instruction is a ________.
๐Ÿ’ป assembly Snippet
mov ax, [0x1234]
  1. A.Fixed displacement (constant offset)
  2. B.Dynamic value stored in a register
  3. C.Sum of base and index registers
  4. D.Value retrieved from the stack
Q13
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Assembly Language InstructionsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In the assembly instruction 'MOV AX, 5', the value 5 serves as which type of operand?
๐Ÿ’ป assembly Snippet
MOV AX, 5
  1. A.source
  2. B.destination
  3. C.memory
  4. D.register
Q14
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Basic Assembly Language InstructionsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In the assembly language instruction 'MOV AX, 5', how many operands are present?
๐Ÿ’ป assembly Snippet
MOV AX, 5
  1. A.2
  2. B.1
  3. C.3
  4. D.4
Q15
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.2. Processor Status and Control FlagsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which group of x86 CPU flags are system control flags and NOT used to reflect the mathematical or arithmetic results of operations?
๐Ÿ’ป assembly Snippet
PUSHF
POPF
  1. A.Direction, Interrupt and Trap flag.
  2. B.Carry, Interrupt and Trap flag.
  3. C.Direction, Overflow and Trap flag.
  4. D.Carry, Zero and Sign flag.
Q16
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.2. Direct AddressingEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Write 8088 assembly language instructions to perform the following memory operations in the current data segment: a. Copy the contents of memory location with offset 0025h into AX. b. Copy register AX into memory location with offset 0FFFh. c. Copy the contents of memory location with offset 0010h to memory location with offset 002Fh.
๐Ÿ’ป assembly Snippet
MOV AX, [0x0025]
Q17
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Addressing Modes and Segment RegistersEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The instruction 'MOV [BP], AL' moves the one-byte content of the AL register to the memory address contained in the BP register within the current ________.
๐Ÿ’ป assembly Snippet
MOV [BP], AL
  1. A.Stack segment
  2. B.Data segment
  3. C.Code segment
  4. D.Extra segment
Q18
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Segmented Memory Architecture and Register PairsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
By default, the Code Segment (CS) register is implicitly paired with which offset register to calculate physical instruction addresses?
  1. A.IP
  2. B.SS
  3. C.BP
  4. D.CX
Q19
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Assembly Language Instruction ConstraintsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In x86 assembly language architecture, direct memory-to-memory operations (e.g., MOV [mem1], [mem2]) are allowed in a single MOV instruction. (True/False)
  1. A.False
  2. B.True
Q20
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 2๐Ÿท๏ธ 2.1. Assembler Syntax and Size Matching RulesEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Attempting to assemble an instruction with mismatched operand sizes (e.g., MOV AX, BL) results in an assembler syntax error. (True/False)
  1. A.True
  2. B.False