Ch 08: String Instructions and Primitives

307 Questions307 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 291 โ€“ 300 of 307 Questions
Page 30 of 31
Q291
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which software interrupt vector is designated for Arithmetic Overflow exceptions (invoked via the INTO instruction)?
๐Ÿ’ป assembly Snippet
into
  1. A.INT 1
  2. B.INT 2
  3. C.INT 3
  4. D.INT 4
Q292
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which low-level system services are provided by ROM BIOS software interrupt vector INT 0x16?
๐Ÿ’ป assembly Snippet
mov ah, 0x00
int 0x16  ; Read character from keyboard
  1. A.Disk services
  2. B.Video services
  3. C.Keyboard services
  4. D.Serial services
Q293
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which instruction returns execution from an Interrupt Service Routine (ISR) by popping IP, then CS, and then the FLAGS register off the stack?
๐Ÿ’ป assembly Snippet
iret
  1. A.RET n
  2. B.REZA
  3. C.REPE
  4. D.IRET
Q294
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which software/hardware interrupt vector is designated for NMI (Non-Maskable Interrupt) in x86 architecture?
  1. A.INT 0
  2. B.INT 1
  3. C.INT 2
  4. D.INT 3
Q295
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.2. Interrupt Vector TableEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
To hook an interrupt in x86 assembly, the programmer alters the corresponding ________ entry inside the Interrupt Vector Table (IVT).
  1. A.SX register
  2. B.Interrupt vector
  3. C.AX register
  4. D.BX register
Q296
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which instruction returns execution from an Interrupt Service Routine (ISR) by popping IP, then CS, and then FLAGS off the stack?
๐Ÿ’ป assembly Snippet
iret
  1. A.RET n
  2. B.REZA
  3. C.REPE
  4. D.IRET
Q297
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which interrupt vector is assigned to NMI (Non-Maskable Interrupt)?
  1. A.INT 0
  2. B.INT 1
  3. C.INT 2
  4. D.INT 3
Q298
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.2. Interrupt Vector TableEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
To hook an interrupt, a programmer must modify the corresponding ________ entry inside the Interrupt Vector Table (IVT).
  1. A.SX register
  2. B.Interrupt vector
  3. C.AX register
  4. D.BX register
Q299
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which instruction returns execution control from an Interrupt Service Routine (ISR) by popping IP, CS, and the FLAGS register sequentially off the stack?
๐Ÿ’ป assembly Snippet
iret
  1. A.RET n
  2. B.REZA
  3. C.REPE
  4. D.IRET
Q300
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ 8.1. Interrupt MechanismEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which interrupt vector is assigned to NMI (Non-Maskable Interrupt) in x86 hardware architecture?
  1. A.INT 0
  2. B.INT 1
  3. C.INT 2
  4. D.INT 3