← CS401 - Computer Architecture and Assembly Language Programming OverviewChapter 8

Ch 08: String Instructions and Primitives

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Showing 131 – 140 of 307 Questions
Page 14 of 31
Q131
❓ MCQ📘 CS401📑 Lec 8🏷️ INTO Instruction and Arithmetic Overflow Interrupt (INT 4)Medium🔁⭐💡📄🎓VU🏛️VU
Which interrupt vector is reserved for handling arithmetic overflow conditions checked via the INTO instruction?
💻 assembly Snippet
into
  1. A.INT 1
  2. B.INT 2
  3. C.INT 3
  4. D.INT 4
Q132
❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC Architecture and IRQ Input LinesMedium🔁⭐💡📄🎓VU🏛️VU
How are the primary Interrupt Request (IRQ) lines on the 8259 Programmable Interrupt Controller (PIC) configured?
  1. A.Eight hardware input interrupt signals
  2. B.One hardware input interrupt signal
  3. C.Eight hardware output interrupt signals
  4. D.One hardware output interrupt signal
Q133
❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC Interrupt Request Priority HierarchyEasy🔁⭐💡📄🎓VU🏛️VU
Among all hardware IRQ lines managed by the master 8259 Programmable Interrupt Controller (PIC), which interrupt request line holds the absolute highest priority level?
  1. A.IRQ 0 (System Timer)
  2. B.IRQ 1 (Keyboard)
  3. C.IRQ 5 (Sound Card / LPT2)
  4. D.IRQ 6 (Floppy Disk)
Q134
❓ MCQ📘 CS401📑 Lec 8🏷️ Hardware Interrupt Requests and IRQ ConflictsEasy🔁⭐💡📄🎓VU🏛️VU
When two hardware peripheral devices in a system attempt to share the same non-shareable Interrupt Request (IRQ) line simultaneously, what condition is created?
  1. A.IRQ collision
  2. B.IRQ conflict
  3. C.IRQ drop
  4. D.IRQ blockage
Q135
❓ MCQ📘 CS401📑 Lec 8🏷️ Divide Error Exception (INT 0)Easy🔁⭐💡📄🎓VU🏛️VU
Which software/hardware processor interrupt vector is automatically triggered when an arithmetic division by zero occurs during DIV or IDIV execution?
💻 assembly Snippet
mov ax, 100
mov bl, 0
div bl
  1. A.Interrupt 0 (INT 0)
  2. B.Interrupt 1 (INT 1)
  3. C.Interrupt 2 (INT 2)
  4. D.Interrupt 3 (INT 3)
Q136
❓ MCQ📘 CS401📑 Lec 8🏷️ Interrupt Service Routine (ISR) ArchitectureEasy🔁⭐💡📄🎓VU🏛️VU
What is the technical term for the software routine that executes in response to a hardware or software interrupt call?
💻 assembly Snippet
my_isr:
    ; Handle interrupt
    iret
  1. A.Interrupt Service Routine (ISR)
  2. B.Interrupt Return Service (IRS)
  3. C.Interrupt Subroutine Program (ISP)
  4. D.Interrupt Routine Table (IRT)
Q137
❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC IRQ Priority HierarchyEasy🔁⭐💡📄🎓VU🏛️VU
Among the hardware interrupt lines managed by the 8259 Programmable Interrupt Controller (PIC), what is the priority level of IRQ 0?
  1. A.Medium
  2. B.High
  3. C.Highest
  4. D.Low
Q138
❓ MCQ📘 CS401📑 Lec 8🏷️ 8259 PIC IRQ Priority HierarchyEasy🔁⭐💡📄🎓VU🏛️VU
Among the hardware Interrupt Request (IRQ) lines managed by the 8259 Programmable Interrupt Controller (PIC), what is the priority level of IRQ 0?
  1. A.low
  2. B.medium
  3. C.highest
  4. D.lowest
Q139
❓ MCQ📘 CS401📑 Lec 8🏷️ Floppy Disk Storage Layout and CapacityEasy🔁⭐💡📄🎓VU🏛️VU
What is the total raw storage capacity of a standard 3.5-inch High-Density (HD) floppy diskette?
  1. A.1444 KB
  2. B.1440 KB
  3. C.1280 KB
  4. D.2480 KB
Q140
❓ MCQ📘 CS401📑 Lec 8🏷️ Port Input/Output Instructions (OUT)Easy🔁⭐💡📄🎓VU🏛️VU
Which CPU register serves as the mandatory source data register for the OUT port I/O instruction?
💻 assembly Snippet
out dx, al
  1. A.AL or AX
  2. B.BL or BX
  3. C.CL or CX
  4. D.DL or DX

📖 Related CS401 - Computer Architecture and Assembly Language Programming Curriculum Units

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View All CS401 - Computer Architecture and Assembly Language Programming Chapters →
Ch 01: Introduction to Assembly Language387 QsCh 02: 16-Bit Segmented Memory Model & Addressing Modes395 QsCh 03: Branching, Loops and Program Flow261 QsCh 04: Bit Manipulation and Shifts198 QsCh 05: Subroutines and Stack Architecture222 QsCh 06: Parameter Passing and Stack Frames216 Qs