Ch 08: String Instructions and Primitives

307 Questions307 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 91 โ€“ 100 of 307 Questions
Page 10 of 31
Q91
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Storage Abstraction Layers: BIOS vs DOSEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which system component provides a higher, more logical view of a storage medium by organizing raw disk sectors into files and directories?
  1. A.BIOS
  2. B.DOS
  3. C.Both BIOS and DOS
  4. D.Hardware Controller
Q92
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Hardware Interrupt Vectors and NMIMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which processor interrupt vector is dedicated as the hardware Non-Maskable Interrupt (NMI) in the x86 architecture?
  1. A.INT 2
  2. B.INT 3
  3. C.INT 0
  4. D.INT 1
Q93
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Programmable Interrupt Controller (PIC) IRQ LinesMediumโญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In standard IBM PC hardware architecture, which Interrupt Request (IRQ) line is assigned to serial communications port COM 2?
  1. A.IRQ 0
  2. B.IRQ 1
  3. C.IRQ 2
  4. D.IRQ 3
Q94
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Programmable Interval Timer (PIT) and INT 8 FrequencyEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is the standard time interval between two consecutive system timer tick interrupts (INT 8) generated by the PIT in an IBM PC?
  1. A.40 ms
  2. B.45 ms
  3. C.50 ms
  4. D.55 ms
Q95
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Single Step Trap Interrupt (INT 1) and CPU ExceptionsMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In 8088 processor architecture, how is the Single-Step Interrupt (INT 1) categorized?
  1. A.Hardware interrupt
  2. B.Like divide by zero interrupt (Internal CPU Exception)
  3. C.Like divide by 1 interrupt
  4. D.Software interrupt
Q96
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Hardware IRQ Assignment and System Timer (IRQ 0)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which Programmable Interrupt Controller (PIC) Interrupt Request (IRQ) line is driven directly by the System Timer (PIT 8253/8254)?
  1. A.IRQ 0
  2. B.IRQ 1
  3. C.IRQ 2
  4. D.IRQ 3
Q97
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Intel 8259 Programmable Interrupt Controller PortsMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In the Intel 8259 Programmable Interrupt Controller (PIC), which I/O port address is designated as the Command/Control port?
๐Ÿ’ป assembly Snippet
mov al, 0x20
out 0x20, al
  1. A.Port 19h
  2. B.Port 20h
  3. C.Port 21h
  4. D.Port 22h
Q98
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ DOS System Interrupt 21h Character Input ServicesEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When calling DOS INT 21h Service 01h (Read Character from Standard Input with Echo), in which register is the read ASCII character returned?
๐Ÿ’ป assembly Snippet
mov ah, 0x01
int 0x21
  1. A.AL
  2. B.BL
  3. C.CL
  4. D.BH
Q99
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Hardware IRQ Interfacing and Keyboard Interrupts (IRQ 1)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which hardware Interrupt Request (IRQ) line is assigned to the keyboard controller in IBM PC/AT architecture?
  1. A.IRQ 0
  2. B.IRQ 1
  3. C.IRQ 2
  4. D.IRQ 3
Q100
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 8๐Ÿท๏ธ Hardware IRQ Assignments for Disk Controllers (IRQ 6)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which hardware Interrupt Request (IRQ) line is assigned to the Floppy Disk Drive controller?
  1. A.IRQ 4
  2. B.IRQ 5
  3. C.IRQ 6
  4. D.IRQ 7