Ch 09: Software Interrupts and DOS/BIOS Services

Covers IVT structure (256 vectors x 4 bytes each = 1KB), pushing flags and CS:IP during interrupt invocation, hooking existing software interrupts, and invoking DOS function calls for disk and character I/O.

174 Questions174 MCQs0 Short Questions0 Long Questions

🎯 Exam Practice Papers

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

Showing 21 – 30 of 174 Questions

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Q21

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (IRQ Conflict Hardware Management)Easy⭐💡📄🎓VU🏛️VU

When two hardware peripheral devices in a computer system attempt to assign and use the same IRQ line, what condition occurs?

A.An IRQ Conflict
B.An IRQ Crash
C.An IRQ Collision
D.An IRQ Blockage

Q22

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (Hardware IRQ Assignments for Serial Ports)Easy🔁⭐💡📄🎓VU🏛️VU

Which hardware interrupt request (IRQ) line is assigned to serial port COM 2 in standard PC architecture?

A.IRQ 0
B.IRQ 1
C.IRQ 2
D.IRQ 3

Q23

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (8259 PIC IRQ Priority Hierarchy)Easy🔁⭐💡📄🎓VU🏛️VU

In the 8259 Programmable Interrupt Controller (PIC) priority hierarchy, what is the priority level of the IRQ 0 (System Timer) interrupt?

A.Highest
B.Low
C.Medium
D.None of the above

Q24

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (Interrupt Execution Mechanics and Register State)Easy🔁⭐💡📄🎓VU🏛️VU

When an interrupt call occurs, the CPU pushes the current register state onto the stack and loads new values into CS, IP, and __________.

A.DS
B.SS
C.FLAGS
D.Bookmark

Q25

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (IRET Interrupt Return Mechanics)Easy🔁⭐💡📄🎓VU🏛️VU

Which instruction returns execution from an Interrupt Service Routine (ISR) by popping IP, then CS, and finally the FLAGS register from the stack?

💻 assembly Snippet

isr_handler:
    ; ISR code
    iret ; Pops IP, CS, FLAGS to return from interrupt

A.RET
B.RET N
C.REPE
D.IRET

Q26

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (INT 1 Trap / Single-Step Interrupt)Easy🔁⭐💡📄🎓VU🏛️VU

Which vector interrupt number in x86 architecture is reserved for the Trap / Single-Step Interrupt used by debuggers?

A.INT 0
B.INT 1
C.INT 2
D.INT 3

Q27

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (INT 2 Non-Maskable Interrupt)Easy🔁⭐💡📄🎓VU🏛️VU

Which vector interrupt number in x86 architecture is assigned to NMI (Non-Maskable Interrupt)?

A.INT 0
B.INT 1
C.INT 2
D.INT 3

Q28

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (Interrupt Hooking and IVT Vector)Easy🔁⭐💡📄🎓VU🏛️VU

To hook an interrupt in x86 assembly, we change the entry in the Interrupt Vector Table (IVT) corresponding to that interrupt __________.

💻 assembly Snippet

; Hooking INT 08h vector in IVT (0x0000:0x0020)
cli
mov word [es:0x0020], new_isr_offset
mov word [es:0x0022], cs
sti

A.SX
B.vector
C.AX
D.BX

Q29

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (IRET Stack Popping Mechanics)Easy🔁⭐💡📄🎓VU🏛️VU

Which x86 assembly instruction restores CPU execution state after an interrupt by popping IP, then CS, and finally the FLAGS register from the stack?

💻 assembly Snippet

custom_isr:
    ; ISR body
    iret ; Pops IP, CS, and FLAGS

A.Ret n
B.REZA
C.REPE
D.IRET

Q30

❓ MCQ📘 CS401📑 Lec 9🏷️ 9.1. Interrupt Handling (INT 1 Trap Interrupt)Easy🔁⭐💡📄🎓VU🏛️VU

Which x86 interrupt vector is designated for the Trap / Single-Step Interrupt used by debugging tools?

A.INT 0
B.INT 1
C.INT 3
D.INT 4

Ch 09: Software Interrupts and DOS/BIOS Services

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

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