Ch 01: Introduction to Assembly Language

387 Questions387 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 241 โ€“ 250 of 387 Questions
Page 25 of 39
Q241
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Why is the system data bus bi-directional?
  1. A.To provide two-way pathing
  2. B.Data moves both from processor to memory (write) and from memory to processor (read)
  3. C.Data moves both from processor to memory and memory to data bus
  4. D.None of the given options
Q242
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Regarding signal direction, how is the control bus categorized overall?
  1. A.It is not important
  2. B.It is important
  3. C.Bi-directional / Multi-directional
  4. D.Unidirectional only
Q243
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
A standard memory cell is an n-bit location used to store data, normally 8 bits wide, which is called a:
  1. A.4-bit (Nibble)
  2. B.8-bit (Byte)
  3. C.6-bit
  4. D.80-bit
Q244
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The number of bits in a single memory cell is called the cell width. Which two dimensions completely define a memory system's capacity?
  1. A.Cell width and number of cells
  2. B.Cell number and width of the cells
  3. C.Width only
  4. D.Height only
Q245
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In memory architecture, two dimensions are defined. Which dimension specifies how many bits are contained within a single memory cell (cell width)?
  1. A.Parallel dimension
  2. B.Vertical dimension
  3. C.Long dimension
  4. D.Short dimension
Q246
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Introduction to Computer ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which operation requires matching sizes between the system data bus width and the memory cell width?
  1. A.Memory access operation (Read/Write)
  2. B.Instruction decode operation
  3. C.Register rotation operation
  4. D.Interrupt handling operation
Q247
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Basic Computer ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which method of memory access operation represents the simplest approach where the system data bus width matches the memory cell width?
  1. A.Normal access
  2. B.Best and simplest access
  3. C.First access
  4. D.None of the given options
Q248
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.1. Basic Computer ArchitectureEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The control bus serves as the physical communication link. Which component is responsible for generating and placing the appropriate control signals onto the control bus?
  1. A.Data Bus
  2. B.Processor
  3. C.Address Bus
  4. D.None of the given options
Q249
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.5. Arithmetic & LogicEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
How many explicit operands does the ADC (Add with Carry) instruction require in assembly language?
๐Ÿ’ป assembly Snippet
adc ax, bx
  1. A.Two operands
  2. B.Three operands
  3. C.Five operands
  4. D.Zero operands
Q250
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 1๐Ÿท๏ธ 1.3. Data MovementEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The fundamental purpose of a computer processor is to perform operations. To perform any operation, the processor requires:
  1. A.Order
  2. B.Nothing
  3. C.Operands
  4. D.Bit