Ch 01: Introduction to Assembly Language

387 Questions387 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

πŸ“˜ VU MID TERM EXAMLectures 1 to 22
⏱️ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

πŸ“30 MCQs
⏱️60 Minutes
πŸ“— VU FINAL TERM EXAMLectures 23 to 45
⏱️ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

πŸ“45 MCQs
⏱️90 Minutes
Showing 111 – 120 of 387 Questions
Page 12 of 39
Q111
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Memory Cell Structure and Byte DefinitionEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
A memory cell is an n-bit location used to store data. In standard computer architecture, what is an 8-bit memory cell normally called?
  1. A.4-bit cell
  2. B.8-bit cell (Byte)
  3. C.6-bit cell
  4. D.80-bit cell
Q112
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Memory Structure DimensionsEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
The number of bits stored in a single memory cell is called cell width. Which two parameters completely define a memory array?
  1. A.Cell width and number of cells
  2. B.Cell number and width of the cells
  3. C.Cell width and height
  4. D.Cell frequency and address depth
Q113
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Memory Cell Width vs Total CellsMediumπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
When organizing memory architecture in two dimensions, which dimension specifies how many bits are contained within a single memory cell?
  1. A.Parallel (Horizontal) dimension
  2. B.Vertical dimension
  3. C.Longitudinal dimension
  4. D.Diagonal dimension
Q114
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Data Bus and Memory Width AlignmentEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
Which condition provides the best and simplest memory access performance in system bus design?
  1. A.Normal operation
  2. B.Best and simplest operation (matching data bus width to memory cell width)
  3. C.Complex operation
  4. D.Indirect operation
Q115
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Processor Control Bus SignalingEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
While the control bus provides the physical signal paths, which hardware component bears the responsibility of issuing control signals over the bus?
  1. A.Data Bus
  2. B.Processor (CPU)
  3. C.Address Bus
  4. D.Memory Controller
Q116
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Memory Architecture DimensionsEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
Which two primary parameters completely define a computer memory's structure and capacity?
  1. A.Cell width and number of cells
  2. B.Cell number and width of the address bus
  3. C.Width and height of processor registers
  4. D.Number of data buses and control lines
Q117
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ System Control Bus DirectionalityEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
How is the system control bus classified in terms of overall signal transmission direction across its lines?
  1. A.It is not important
  2. B.Unidirectional
  3. C.Bidirectional
  4. D.None of the given options
Q118
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Memory Cell Width and Byte DefinitionEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
A standard memory cell is an n-bit location used to store data, commonly referred to as a byte. What is the value of n for a byte?
  1. A.4-bit
  2. B.8-bit
  3. C.16-bit
  4. D.80-bit
Q119
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Data Bus Width Matching and Memory TransfersEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
In computer hardware design, what relationship between the data bus and memory cells yields the best and simplest memory transfers?
  1. A.Normal operation
  2. B.When the data bus size matches the memory cell width
  3. C.When the data bus size is double the cell width
  4. D.None of the given options
Q120
❓ MCQπŸ“˜ CS401πŸ“‘ Lec 1🏷️ Memory Parallel and Vertical DimensionsEasyπŸ”β­πŸ’‘πŸ“„πŸŽ“VUπŸ›οΈVU
When defining memory dimensions, what does the parallel (horizontal) dimension specify?
  1. A.How many bits are in a single memory cell (cell width)
  2. B.How many total memory addresses exist in memory
  3. C.The length of the physical address bus
  4. D.The number of instruction cycles per access