← CS401 - Computer Architecture and Assembly Language Programming OverviewChapter 16

Ch 16: Interfacing Assembly with C/C++

69 Questions69 MCQs0 Short Questions0 Long Questions
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Showing 51 – 60 of 69 Questions
Page 6 of 7
Q51
❓ MCQ📘 CS401📑 Lec 16🏷️ Little-Endian Video RAM Byte PlacementEasy🔁⭐💡📄🎓VU🏛️VU
Why does executing 'mov word [es:0], 0x0741' display the letter 'A' with light gray attribute 0x07 at the top-left corner of the screen?
💻 assembly Snippet
mov word [es:0], 0x0741
  1. A.Because the 8088 is little-endian, storing the low byte 0x41 ('A') at offset 0 and the high byte 0x07 (attribute) at offset 1
  2. B.Because the 8088 is big-endian, storing 0x07 at offset 0 and 0x41 at offset 1
  3. C.Because the ES segment register automatically swaps ASCII and attribute bytes
  4. D.Because 0x0741 is an extended ASCII character code representing the letter 'A'
Q52
📝 Short Q📘 CS401📑 Lec 16🏷️ Segment Register Loading Constraints and Little-Endian Video RAM WritesMedium🔁⭐💡📄🎓VU🏛️VU
Why is 'mov es, 0xB800' an illegal instruction in 8088 assembly language, and how does little-endian word storage affect writing 'mov word [es:0], 0x0741' to display character 'A' on screen?
💻 assembly Snippet
mov ax, 0xb800
mov es, ax
mov word [es:0], 0x0741
Q53
❓ MCQ📘 CS401📑 Lec 16🏷️ IDTR Register and Protected Mode IDTMedium⭐💡📄🎓VU🏛️VU
In x86 protected mode architecture, the base physical address and size limit of the IDT (Interrupt Descriptor Table) are stored in which CPU register?
💻 assembly Snippet
sidt [idt_ptr]
lidt [idt_ptr]
  1. A.GDTR
  2. B.IDTR
  3. C.IVT
  4. D.IDTT
Q54
❓ MCQ📘 CS401📑 Lec 16🏷️ Motorola 68K 32-Bit Register ArchitectureEasy⭐💡📄🎓VU🏛️VU
Motorola 68K family microprocessors feature general-purpose registers (D0–D7, A0–A7) that have a bit width of:
  1. A.4 bits
  2. B.8 bits
  3. C.16 bits
  4. D.32 bits
Q55
❓ MCQ📘 CS401📑 Lec 16🏷️ 32-Bit Address Register Physical Memory Capacity (4 GB)Easy⭐💡📄🎓VU🏛️VU
In 32-bit x86 architecture (such as the 80386), a 32-bit address register can directly access up to how much physical memory space?
  1. A.2 GB
  2. B.4 GB
  3. C.6 GB
  4. D.8 GB
Q56
❓ MCQ📘 CS401📑 Lec 16🏷️ 32-Bit Address Space Capacity (4 GB)Easy🔁⭐💡📄🎓VU🏛️VU
A 32-bit address register can generate unique physical memory addresses to directly access up to how much memory?
  1. A.2 GB
  2. B.4 GB
  3. C.6 GB
  4. D.8 GB
Q57
❓ MCQ📘 CS401📑 Lec 16🏷️ NASM EXTERN and GLOBAL DirectivesEasy🔁⭐💡📄🎓VU🏛️VU
In NASM assembly language, an imported external symbol is declared using the ________ directive, while an exported symbol is declared using the ________ directive.
💻 assembly Snippet
extern my_ext_func
global my_export_func
  1. A.Global directive, External directive
  2. B.External directive, Global directive
  3. C.Home directive, Foreign directive
  4. D.Foreign directive, Home directive
Q58
❓ MCQ📘 CS401📑 Lec 16🏷️ 32-Bit Address Register Physical Memory Capacity (4 GB)Easy🔁⭐💡📄🎓VU🏛️VU
A 32-bit address register can generate unique addresses to directly access up to how much memory?
  1. A.2 GB
  2. B.4 GB
  3. C.6 GB
  4. D.8 GB
Q59
❓ MCQ📘 CS401📑 Lec 16🏷️ 32-Bit Address Register Memory Capacity (4 GB)Easy🔁⭐💡📄🎓VU🏛️VU
A 32-bit address register can generate unique physical memory addresses to directly access up to how much memory space?
  1. A.2 MB
  2. B.2 GB
  3. C.4 MB
  4. D.4 GB
Q60
❓ MCQ📘 CS401📑 Lec 16🏷️ IDTR Register and Protected Mode IDTMedium🔁⭐💡📄🎓VU🏛️VU
In x86 protected mode architecture, the physical base address and limit of the Interrupt Descriptor Table (IDT) are stored in which CPU register?
💻 assembly Snippet
lidt [idt_ptr]
  1. A.GDTR
  2. B.IDTR
  3. C.IVT
  4. D.IDTT

📖 Related CS401 - Computer Architecture and Assembly Language Programming Curriculum Units

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View All CS401 - Computer Architecture and Assembly Language Programming Chapters →
Ch 01: Introduction to Assembly Language387 QsCh 02: 16-Bit Segmented Memory Model & Addressing Modes395 QsCh 03: Branching, Loops and Program Flow261 QsCh 04: Bit Manipulation and Shifts198 QsCh 05: Subroutines and Stack Architecture222 QsCh 06: Parameter Passing and Stack Frames216 Qs