Ch 16: Interfacing Assembly with C/C++

Practical guide to mixed-language programming, writing assembly subroutines callable from C, passing pointer arguments, accessing struct members in assembly, and inline assembly syntax.

69 Questions69 MCQs0 Short Questions0 Long Questions

🎯 Exam Practice Papers

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

Showing 31 – 40 of 69 Questions

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Q31

❓ MCQ📘 CS401📑 Lec 16🏷️ RISC Architecture and SPARC Instruction FormattingMedium🔁⭐💡📄🎓VU🏛️VU

What is the fixed instruction size utilized by the Sun SPARC RISC processor architecture?

A.16-bit
B.32-bit
C.64-bit
D.20-bit

Q32

❓ MCQ📘 CS401📑 Lec 16🏷️ RISC Architecture vs CISC Architecture (SPARC 32-bit Instructions)Medium🔁⭐💡📄🎓VU🏛️VU

The Sun SPARC RISC processor architecture utilizes a fixed instruction encoding size of __________.

A.16-bit
B.32-bit
C.64-bit
D.20-bit

Q33

❓ MCQ📘 CS401📑 Lec 16🏷️ Motorola 68K Architecture and Program CounterEasy🔁⭐💡📄🎓VU🏛️VU

In Motorola 68K processors, which 32-bit register holds the memory address of the currently executing instruction?

A.Program counter (PC)
B.Stack pointer (SP)
C.Register
D.Stack

Q34

❓ MCQ📘 CS401📑 Lec 16🏷️ Motorola 68K Architecture and Program Counter WidthEasy🔁⭐💡📄🎓VU🏛️VU

In Motorola 68K processors, the Program Counter (PC) that holds the memory address of the currently executing instruction is how many bits wide?

A.8 bits
B.16 bits
C.32 bits
D.64 bits

Q35

❓ MCQ📘 CS401📑 Lec 16🏷️ Motorola 68K Register Set ArchitectureEasy🔁⭐💡📄🎓VU🏛️VU

Motorola 68K microprocessors feature how many 32-bit general-purpose registers?

A.4 registers
B.8 registers
C.16 registers
D.32 registers

Q36

❓ MCQ📘 CS401📑 Lec 16🏷️ Cache Memory Mechanics (Cache Hit vs Cache Miss)Easy🔁⭐💡📄🎓VU🏛️VU

Which of the following best describes a 'cache hit' in computer memory hierarchy?

A.When requested data is successfully found in the high-speed cache memory
B.When data is removed or evicted from the cache memory
C.The total number of times the cache is accessed directly by the processor
D.When requested data is missing from the cache memory

Q37

📝 Short Q📘 CS401📑 Lec 16🏷️ Motorola 68K Instruction Set (Data Movement and Arithmetic)Hard🔁⭐💡📄🎓VU🏛️VU

List and categorize key Data Movement and Arithmetic instructions available in the Motorola 68K processor architecture.

💻 assembly Snippet

MOVE.L D0, D1
ADD.L D2, D1

Q38

❓ MCQ📘 CS401📑 Lec 16🏷️ Motorola 68K Register Set ArchitectureEasy🔁⭐💡📄🎓VU🏛️VU

Motorola 68K processors feature how many 32-bit general-purpose registers?

A.4 registers
B.8 registers
C.16 registers
D.32 registers

Q39

📝 Short Q📘 CS401📑 Lec 16🏷️ ASCII Character Encoding (Standard 7-bit vs IBM Extended 8-bit ASCII)Easy🔁⭐💡📄🎓VU🏛️VU

What does ASCII stand for, and how does standard 7-bit ASCII differ from Extended 8-bit IBM PC ASCII?

Q40

📝 Short Q📘 CS401📑 Lec 16🏷️ Display Memory (Video RAM Base 0xB800 and Memory-Mapped Video Output)Easy🔁⭐💡📄🎓VU🏛️VU

Explain the concept of Display Memory (Video RAM) in 8088 PC architecture and state why text mode display memory starts at physical segment base 0xB800.

💻 assembly Snippet

mov ax, 0xb800
mov es, ax
mov byte [es:0], 'A'
mov byte [es:1], 0x07

Ch 16: Interfacing Assembly with C/C++

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

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