Ch 03: Branching, Loops and Program Flow

261 Questions261 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
SEMESTER PASS

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 141 โ€“ 150 of 261 Questions
Page 15 of 27
Q141
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (Operand Count in MOV Instruction)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In the assembly language instruction `MOV AX, 5`, how many total operands are present?
๐Ÿ’ป assembly Snippet
mov ax, 5 ; 2 operands: AX (destination) and 5 (source)
  1. A.1
  2. B.2
  3. C.3
  4. D.4
Q142
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Register Architecture (Control Flags vs Status Flags)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which group of processor flags consists solely of control flags rather than status flags used for mathematical and arithmetic operations?
  1. A.Carry, Interrupt and Trap flag.
  2. B.Direction, Interrupt and Trap flag.
  3. C.Direction, Overflow and Trap flag.
  4. D.Direction, Interrupt and Sign flag.
Q143
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (COM File ORG 0x0100 Origin Offset)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In MS-DOS, the entry point and first executable instruction of a `.COM` executable file must be located at offset address:
๐Ÿ’ป assembly Snippet
[org 0x0100] ; Mandated starting offset for DOS COM executables
  1. A.0x0010
  2. B.0x0100
  3. C.0x1000
  4. D.0x0000
Q144
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (DIV 8-Bit and 16-Bit Division Forms)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In 8088 16-bit architecture, the unsigned integer division instruction `DIV` has how many primary operand forms?
๐Ÿ’ป assembly Snippet
; Form 1 (8-bit):  div bl  ; AX / BL -> Quotient AL, Remainder AH
; Form 2 (16-bit): div bx  ; DX:AX / BX -> Quotient AX, Remainder DX
  1. A.Two forms
  2. B.Three forms
  3. C.Four forms
  4. D.Five forms
Q145
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (16-Bit DIV Implied 32-Bit Dividend in DX:AX)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the divisor operand of a `DIV` instruction is a 16-bit word, how many bits wide is the implied dividend?
๐Ÿ’ป assembly Snippet
div cx ; 32-bit dividend in DX:AX divided by 16-bit divisor in CX
  1. A.8 bits
  2. B.16 bits
  3. C.32 bits
  4. D.64 bits
Q146
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ 3.1. Basic Assembly Instructions (Divide Overflow Error Mechanics)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a division operation calculates a quotient that exceeds the destination register capacity (for example, dividing a large dividend by a very small divisor), what error condition is generated?
  1. A.Divide logical error
  2. B.Divide overflow error
  3. C.Divide syntax error
  4. D.An illegal instruction
Q147
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ Arithmetic Instructions and Flag OperationsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Describe the internal operations performed by the CMP (Compare) instruction in the 8088 microprocessor.
๐Ÿ’ป assembly Snippet
cmp ax, bx
Q148
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ Unsigned Division and Register PairingMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the divisor operand of an unsigned division (DIV) instruction is 16 bits wide, where is the implied 32-bit dividend stored?
๐Ÿ’ป assembly Snippet
mov dx, 0      ; Clear high word of dividend
mov ax, 500    ; Low word of dividend in AX
mov bx, 10     ; 16-bit divisor in BX
div bx         ; Divides DX:AX by BX
  1. A.AX register
  2. B.The concatenation of DX and AX
  3. C.The concatenation of ES and AX
  4. D.The concatenation of DS and BX
Q149
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ Bitwise Shifts and Arithmetical DivisionEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Provide valid and efficient 8088 assembly instruction(s) to divide the value stored in register AX by 8.
๐Ÿ’ป assembly Snippet
mov cl, 3
shr ax, cl
Q150
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 3๐Ÿท๏ธ Logical vs Arithmetic Shift InstructionsMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Differentiate between the SHR (Shift Logical Right) and SAR (Shift Arithmetic Right) instructions in 8088 assembly language.
๐Ÿ’ป assembly Snippet
shr ax, 1
sar bx, 1