Ch 15: 32-Bit Protected Mode Architecture

Define Protected Mode in x86 architecture and explain how it is enabled and its memory addressing capabilities.

mov eax, cr0
or eax, 1
mov cr0, eax

Read the following passage regarding x86 Segment Descriptors in Protected Mode and fill in the missing terms: 'In descriptors, the 32-bit base is scattered into different places for backward compatibility. The limit is stored in 20 bits, but the [Blank 1] defines whether the limit is in terms of single bytes or 4 KB pages, allowing a maximum segment size of 4 GB. The [Blank 2] bit must be set to signal that this segment is currently present in physical RAM. DPL is the Descriptor Privilege Level, defining protection levels (0-3).'

Read the passage carefully and fill in the blanks with the correct segment descriptor attribute bits (G bit, P bit, D bit, C bit, R bit, A bit): 'In descriptors, the 32-bit base address is scattered across different fields for backward compatibility. The limit is stored in 20 bits, but the [Blank 1] defines whether the limit is in terms of bytes or 4 KB pages (allowing up to 4 GB). The [Blank 2] must be set to signal that the segment is present in memory. DPL is the Descriptor Privilege Level. The [Blank 3] defines whether the segment executes code in 16-bit or 32-bit mode. The [Blank 4] is the conforming bit. The [Blank 5] signals that the segment is readable, and the [Blank 6] is automatically set whenever the segment is accessed.'

In x86 Protected Mode, what information is stored in the first 16 bits (bits 0–15) of an 8-byte Segment Descriptor?

Give the names and primary functions of any two segment descriptors used in x86 Protected Mode architecture.