Ch 12: Terminate and Stay Resident (TSR)

In-depth study of writing Terminate and Stay Resident (TSR) programs in assembly, preserving resident memory blocks, intercepting keyboard scancodes via INT 09h, and unhooking interrupt vectors cleanly.

127 Questions127 MCQs0 Short Questions0 Long Questions

🎯 Exam Practice Papers

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

Showing 101 – 110 of 127 Questions

Page 11 of 13

Q101

❓ MCQ📘 CS401📑 Lec 12🏷️ 8259 PIC Interrupt Mask Register Port (0x21)Medium🔁⭐💡📄🎓VU🏛️VU

In the 8259 Programmable Interrupt Controller (PIC), which I/O port address acts as the Interrupt Mask Register (IMR) for enabling or disabling individual hardware IRQs?

💻 assembly Snippet

in al, 0x21

A.Port 21 (0x21)
B.Port 20 (0x20)
C.Port 60 (0x60)
D.Port 61 (0x61)

Q102

❓ MCQ📘 CS401📑 Lec 12🏷️ 8259 PIC Hardware Pin ArchitectureEasy🔁⭐💡📄🎓VU🏛️VU

In the 8259 Programmable Interrupt Controller (PIC) hardware interface, the IRQ signal interface consists of:

A.Eight input signals and one output signal
B.One input signal and one output signal
C.Eight input signals and eight output signals
D.One input signal and eight output signals

Q103

❓ MCQ📘 CS401📑 Lec 12🏷️ Trap Flag (TF) Modification MechanicsMedium🔁⭐💡📄🎓VU🏛️VU

Which CPU flag has no dedicated assembly instruction to clear it directly (unlike CLI for IF or CLD for DF)?

💻 assembly Snippet

pushf
pop ax
and ax, 0xFEFF  ; Clear bit 8 (TF)
push ax
popf

A.Trap flag (TF)
B.Interrupt flag (IF)
C.Direction flag (DF)
D.None of the above

Q104

❓ MCQ📘 CS401📑 Lec 12🏷️ End of Interrupt (EOI) Signaling to 8259 PICEasy🔁⭐💡📄🎓VU🏛️VU

An End of Interrupt (EOI) command signal is sent by the Interrupt Service Routine (Handler) to the:

💻 assembly Snippet

mov al, 0x20
out 0x20, al  ; Send EOI to PIC

A.Handler
B.Processor
C.IRQ line
D.Programmable Interrupt Controller (PIC)

Q105

❓ MCQ📘 CS401📑 Lec 12🏷️ IRQ 0 Programmable Interval Timer InterruptEasy🔁⭐💡📄🎓VU🏛️VU

Which hardware IRQ (Interrupt Request) line is generated by the system timer device (8254 PIT)?

A.IRQ 0
B.IRQ 1
C.IRQ 2
D.IRQ 3

Q106

❓ MCQ📘 CS401📑 Lec 12🏷️ 8259 PIC Interrupt Mask Register Port (0x21)Medium🔁⭐💡📄🎓VU🏛️VU

The 8259 Programmable Interrupt Controller (PIC) utilizes I/O ports 0x20 and 0x21. Port 0x20 is the Control port, while Port 0x21 is the:

💻 assembly Snippet

in al, 0x21
or al, 0x01   ; Mask IRQ 0
out 0x21, al

A.Interrupt Mask Register (IMR) port
B.Interrupt port
C.Output port
D.Input port

Q107

❓ MCQ📘 CS401📑 Lec 12🏷️ 8259 PIC Interrupt Mask Register Port (0x21)Medium🔁⭐💡📄🎓VU🏛️VU

In the 8259 Programmable Interrupt Controller (PIC), which I/O port address functions as the Interrupt Mask Register (IMR)?

💻 assembly Snippet

in al, 0x21

A.19
B.20
C.21
D.22

Q108

❓ MCQ📘 CS401📑 Lec 12🏷️ Keyboard Hardware Port 0x60 InputEasy🔁⭐💡📄🎓VU🏛️VU

Which assembly instruction is used to read a scan code character from the PC keyboard controller data port (I/O port 0x60)?

💻 assembly Snippet

in al, 0x60

A.in al, 0x60
B.out al, 0x60
C.in al, 0x80
D.out al, 0x80

Q109

❓ MCQ📘 CS401📑 Lec 12🏷️ x86 Interrupt Vector Priority Ranking (INT 0)Easy🔁⭐💡📄🎓VU🏛️VU

Among the CPU interrupt vectors listed below, which possesses the highest architectural priority?

A.INT 3
B.INT 2
C.INT 1
D.INT 0

Q110

❓ MCQ📘 CS401📑 Lec 12🏷️ 8259 PIC Interrupt Mask Register Port (0x21)Medium🔁⭐💡📄🎓VU🏛️VU

In the 8259 Programmable Interrupt Controller (PIC), which I/O port address is used for selectively enabling or disabling individual hardware interrupts?

💻 assembly Snippet

in al, 0x21
or al, 0x01   ; Mask IRQ 0
out 0x21, al

A.19
B.20
C.21
D.22

Ch 12: Terminate and Stay Resident (TSR)

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Mid Term Examination

Final Term Examination

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