Ch 17: Secondary Storage and Device Drivers

183 Questions183 MCQs0 Short Questions0 Long Questions
๐ŸŽฏ Exam Practice Papers
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
โฑ๏ธ90 Minutes
Showing 61 โ€“ 70 of 183 Questions
Page 7 of 19
Q61
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ System Bus Directionality and FunctionalityEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which of the following statements accurately describes the directionality and primary role of the Address Bus and Data Bus in a computer system?
  1. A.The Address Bus is unidirectional (CPU to peripherals) for selecting memory locations, while the Data Bus is bidirectional for transferring data
  2. B.The Address Bus is bidirectional for transferring addresses, while the Data Bus is unidirectional from peripherals to CPU
  3. C.Both the Address Bus and Data Bus are strictly unidirectional from CPU to external peripherals
  4. D.The Address Bus carries Control Signals like Memory Read, while the Data Bus specifies physical memory locations
Q62
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ Interrupt Request (IRQ) Lines and Hardware IRQ ConflictsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When two hardware expansion devices in a PC system attempt to use the same physical IRQ line simultaneously without bus-sharing support, what condition occurs?
  1. A.An IRQ Conflict
  2. B.An IRQ Crash
  3. C.An IRQ Collision
  4. D.An IRQ Blockage
Q63
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ Processor Memory Communication via System BusesMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain step-by-step how the processor uses the address bus, data bus, and control bus to communicate with system memory during read and write operations.
Q64
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ Control Bus Signal Operations (MEMR, MEMW, IOR, IOW)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
List the four fundamental control signals transmitted over the system Control Bus and explain their respective functions in memory and I/O operations.
Q65
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ Hard Disk Master Boot Record (MBR) Structure and Sector SizeEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is the standard total physical sector size of the Master Boot Record (MBR) on an IBM PC compatible hard disk drive?
  1. A.446 bytes
  2. B.350 bytes
  3. C.512 bytes
  4. D.256 bytes
Q66
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ Hardware IRQ Assignments for Serial COM PortsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which standard hardware IRQ interrupt line is assigned to serial communications port COM 2 in PC architecture?
  1. A.IRQ 0
  2. B.IRQ 1
  3. C.IRQ 2
  4. D.IRQ 3
Q67
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ Hard Disk First Sector Layout (MBR and Partition Table)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What critical system data structures are contained within the first sector (LBA 0) of a partitioned hard disk drive?
  1. A.Master Boot Record (MBR) and Primary Partition Table
  2. B.File Allocation Table (FAT) and Root Directory
  3. C.Operating System Kernel and Swap File
  4. D.BIOS Interrupt Vector Table and Stack Frame
Q68
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ 8259 Programmable Interrupt Controller (PIC) I/O Port MappingEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
In the 8259 Programmable Interrupt Controller (PIC 1), which I/O port address is referred to as the Control/Command port?
๐Ÿ’ป assembly Snippet
out 0x20, al
  1. A.19
  2. B.20
  3. C.21
  4. D.22
Q69
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ Hardware IRQ Assignments for Parallel LPT PortsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Which hardware IRQ interrupt line is assigned to the primary parallel printer port (LPT1) in standard IBM PC architecture?
  1. A.IRQ 4
  2. B.IRQ 5
  3. C.IRQ 6
  4. D.IRQ 7
Q70
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 17๐Ÿท๏ธ Programmable Interval Timer (PIT) Input FrequencyEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
What is the input clock frequency supplied to the 8253/8254 Programmable Interval Timer (PIT) chip in IBM PC compatible systems?
  1. A.1.193 MHz
  2. B.2.193 MHz
  3. C.3.193 MHz
  4. D.4.193 MHz