Ch 04: Bit Manipulation and Shifts

198 Questions198 MCQs0 Short Questions0 Long Questions
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CS401 - Computer Architecture and Assembly Language Programming Examination Practice

Timed practice exam simulation for CS401 - Computer Architecture and Assembly Language Programming.

๐Ÿ“˜ VU MID TERM EXAMLectures 1 to 22
โฑ๏ธ 60 Mins

Mid Term Examination

Covers syllabus of Lectures 1 to 22 with 30 high-yield MCQs in a timed exam environment.

๐Ÿ“30 MCQs
โฑ๏ธ60 Minutes
๐Ÿ“— VU FINAL TERM EXAMLectures 23 to 45
โฑ๏ธ 90 Mins

Final Term Examination

Comprehensive semester exam preparation with 45 MCQs covering Lectures 23 to 45 with complete course coverage.

๐Ÿ“45 MCQs
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Showing 151 โ€“ 160 of 198 Questions
Page 16 of 20
Q151
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Rotate Through Carry Right (RCR) MechanicsMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When a Rotate Through Carry Right (RCR) instruction is applied to a 16-bit word, how many total bits participate in the circular rotation?
๐Ÿ’ป assembly Snippet
rcr ax, 1
  1. A.16 bits rotation
  2. B.1 bit rotation
  3. C.17 bits rotation
  4. D.8 bits rotation
Q152
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Bitwise Shift Right MechanicsEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Suppose the decimal number 35 is shifted to the right by 1 bit position in binary (or 35 >> 1); what is the resulting decimal value?
๐Ÿ’ป assembly Snippet
mov al, 35
shr al, 1
  1. A.35
  2. B.70
  3. C.140
  4. D.17
Q153
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Bitwise Shift Logical Right (SHR) DiagramMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The bit shift diagram '0 --> [ 1 | 1 | 0 | 1 | 0 | 0 | 0 ] --> C' represents which assembly shift instruction?
๐Ÿ’ป assembly Snippet
shr al, 1
  1. A.SHL (Shift Logical Left)
  2. B.SAR (Shift Arithmetic Right)
  3. C.SHR (Shift Logical Right)
  4. D.SAL (Shift Arithmetic Left)
Q154
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Bitwise Shift Logical Left (SHL) DiagramMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
The bit shift diagram 'C <-- [ 1 | 1 | 0 | 1 | 0 | 0 | 0 ] <-- 0' represents which assembly shift instruction?
๐Ÿ’ป assembly Snippet
shl al, 1
  1. A.SHL (Shift Logical Left)
  2. B.SAR (Shift Arithmetic Right)
  3. C.SHR (Shift Logical Right)
  4. D.SAL (Shift Arithmetic Left)
Q155
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Bitwise Logic Instructions (AND)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When the instruction 'AND AX, BX' is executed on 16-bit registers, how many bitwise AND operations are performed simultaneously?
๐Ÿ’ป assembly Snippet
and ax, bx
  1. A.16 AND operations
  2. B.17 AND operations
  3. C.32 AND operations
  4. D.8 AND operations
Q156
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Shift Instructions (SHR vs SAL)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Are SHR (Shift Logical Right) and SAL (Shift Arithmetic Left) identical instructions in assembly language?
๐Ÿ’ป assembly Snippet
shr ax, 1
sal ax, 1
  1. A.True
  2. B.False
Q157
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Bitwise Rotate Right (ROR) InstructionMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain the operation and functionality of the ROR (Rotate Right) instruction in x86 assembly language.
๐Ÿ’ป assembly Snippet
ror ax, 1
Q158
๐Ÿ“ Short Q๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Difference Between SHR and SAR InstructionsMedium๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
Explain the fundamental difference between the SHR (Shift Logical Right) and SAR (Shift Arithmetic Right) instructions in x86 assembly language.
๐Ÿ’ป assembly Snippet
shr al, 1
sar bl, 1
Q159
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ Bitwise Shift Left (SHL) Instruction and MultiplicationEasy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
If register AL contains the decimal value 5, performing two logical left shift operations (SHL AL, 2) produces what decimal value?
๐Ÿ’ป assembly Snippet
mov al, 5
shl al, 2
  1. A.5
  2. B.10
  3. C.15
  4. D.20
Q160
โ“ MCQ๐Ÿ“˜ CS401๐Ÿ“‘ Lec 4๐Ÿท๏ธ DIV Instruction Operands (8-Bit Division)Easy๐Ÿ”โญ๐Ÿ’ก๐Ÿ“„๐ŸŽ“VU๐Ÿ›๏ธVU
When executing the 8-bit division instruction 'DIV BL', where must the implied 16-bit dividend be stored prior to execution?
๐Ÿ’ป assembly Snippet
div bl
  1. A.AX register
  2. B.BX register
  3. C.CX register
  4. D.DX register