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Lecture 8: Branching

261 Questions205 MCQs51 Short Questions5 Long Questions
Showing 111 – 120 of 261 Questions
Page 12 of 27
Q111❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
When executing a 16-bit division instruction (`DIV reg16`), dividing a 32-bit dividend in `DX:AX` by a 16-bit operand, what is the bit width of the resulting quotient stored in register `AX`?
💻 assembly Snippet
div bx ; Divides DX:AX by BX; Quotient in AX (16-bit), Remainder in DX (16-bit)
  1. A.4 bits
  2. B.32 bits
  3. C.16 bits
  4. D.8 bits
Q112❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
When executing an 8-bit division instruction (`DIV reg8`), dividing a 16-bit dividend in register `AX` by an 8-bit operand, in which register is the resulting quotient stored?
💻 assembly Snippet
div bl ; Divides AX by BL; Quotient in AL, Remainder in AH
  1. A.AL
  2. B.AX
  3. C.AH
  4. D.DX
Q113📝 Short Q📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
Define what an implied operand is in assembly language instructions and give an example.
💻 assembly Snippet
mul bl ; BL is explicit operand; AL and AX are implied operands
Q114❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
When performing 16-bit division using `DIV reg16`, where is the 32-bit implied dividend operand stored?
💻 assembly Snippet
div bx ; Divides 32-bit dividend DX:AX by 16-bit register BX
  1. A.AX register
  2. B.The concatenation of DX and AX
  3. C.The concatenation of ES and AX
  4. D.The concatenation of DS and BX
Q115❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
When the operand of a `DIV` instruction is a 16-bit register or memory location (`DIV reg16`), what is the required bit size of the implied dividend operand (`DX:AX`)?
💻 assembly Snippet
div bx ; Divides 32-bit dividend in DX:AX by 16-bit operand BX
  1. A.32 bit
  2. B.64 bit
  3. C.16 bit
  4. D.8 bit
Q116❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
True or False: A 'Size Mismatch' error (e.g., trying to move an 8-bit register value into a 16-bit register, such as `mov ax, bl`) is classified as an assembler syntax error.
💻 assembly Snippet
mov ax, bl ; Syntax Error: Size Mismatch (16-bit destination, 8-bit source)
  1. A.False
  2. B.True
Q117❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
In x86 CPU architecture, which register contains individual bit flags where each single bit specifies a distinct status or control condition?
  1. A.Accumulator Register
  2. B.Pointer Register
  3. C.Index register
  4. D.Flag register
Q118❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
True or False: Direct memory-to-memory data transfer operations (e.g., `MOV [mem1], [mem2]`) are permitted in standard x86 `MOV` instruction syntax.
💻 assembly Snippet
; mov [num1], [num2] ; ILLEGAL in x86 ISA
mov ax, [num2]
mov [num1], ax      ; Legal two-step transfer
  1. A.True
  2. B.False
Q119❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
In x86 assembly language, machine opcode `0x90` corresponds to which instruction?
💻 assembly Snippet
nop ; Machine opcode 0x90 (No Operation / Do nothing)
  1. A.Do nothing (NOP)
  2. B.Add
  3. C.Subtract
  4. D.Multiplication
Q120❓ MCQ📑 Lec 3Easy🔁Repeated⭐High-Yield💡Conceptual
In x86 processor architecture, which register consists of individual bit positions where each single bit specifies a distinct status or control meaning?
  1. A.Accumulator Register
  2. B.Pointer Register
  3. C.Index register
  4. D.Flag register

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Introduction to Assembly Language 1PracticeIntroduction to Assembly Language 2PracticeIntroduction to Assembly Language 3PracticeSegmented Memory ModelPracticeData Declaration and Direct AddressingPracticeIndirect AddressingPractice